Clock Frequency Stepping to Limit Supply Voltage Drop
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Solution Overview
Problem
Existing methods for dynamically varying the clock frequency of current consumers operated in a clocked manner face challenges in maintaining operational stability due to voltage drops or overvoltage issues, requiring large and expensive voltage regulators to handle worst-case scenarios, which limits frequency change speed and efficiency.
Innovation Solution
A frequency regulator that performs clock frequency variations through a series of non-linear changes, each with different amounts, adapting to the power supply's characteristics to minimize voltage or power instabilities and allow faster frequency changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased jump-wise from the current actual frequency to the set frequency, then the frequency change speed is maximized, but the voltage drop becomes so strong that the minimum supply voltage is fallen below, causing the current consumer to become non-functional
Solution Approach 1:
The patent divides a single large frequency jump into multiple smaller incremental steps. Instead of changing frequency from f1 directly to f2 in one step, the system performs intermediate changes (f1→f1.5→f2), allowing the voltage regulator to stabilize at each step and preventing excessive voltage drops that would occur with a single large jump.
Solution Approach 2:
The patent implements dynamic adaptation of the frequency change strategy based on system state. The control mechanism monitors voltage regulator performance and dynamically adjusts the frequency increment size, switching between jump-wise changes (when voltage stability allows) and incremental changes (when voltage drop risk is high), optimizing both speed and reliability.
2Reliability
If the clock frequency is increased linearly in several equidistant steps, then the voltage drop is reduced compared to jump-wise switching, but the frequency change speed becomes lower than the maximum possible speed
Solution Approach 1:
The patent applies different frequency increment sizes to different operating conditions. When the voltage regulator is performing well and headroom is available, larger frequency steps are used. When the regulator is stressed or voltage drop is detected, smaller incremental steps are applied. This local adaptation of step size optimizes both speed and stability for each specific system state.
Solution Approach 2:
The system implements feedback control by monitoring the voltage regulator's performance during frequency transitions. Based on this feedback, the control mechanism dynamically adjusts subsequent frequency change steps, slowing down when voltage instability is detected and accelerating when stability is confirmed, thereby achieving optimal balance between speed and reliability.
3Reliability
If large and expensive voltage regulators are used to handle worst-case scenarios, then operational stability is ensured, but device complexity and cost increase
Solution Approach 1:
The patent performs preliminary frequency adjustments before critical voltage drops occur. By proactively managing frequency transitions and anticipating voltage regulator limitations, the system prevents worst-case scenarios from occurring, allowing the use of smaller, less expensive voltage regulators that would otherwise be overwhelmed by unmanaged frequency jumps.
Solution Approach 2:
The patent converts the potential harm of voltage drops into a beneficial control mechanism. By deliberately implementing controlled, incremental frequency changes that generate manageable voltage transitions, the system transforms what would be a harmful effect (voltage drop) into a predictable, controllable parameter that enables the use of simpler, cheaper voltage regulators.
Data Source
AI summary
A frequency regulator for varying a clock frequency of a power-supplied consumer operated in a clocked manner, wherein the frequency regulator is implemented to perform an overall variation of the clock frequency from an actual frequency to a set frequency, such that the overall variation is obtained by a plurality of clock changes, each with a different amount of change, wherein each of the respective amounts of change depends on a power change caused by the associated clock frequency change.