Clock Frequency Recovery Control During SoC Voltage Drops
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Solution Overview
Problem
In systems-on-a-chip (SoC), instantaneous voltage drops can lead to insufficient timing, causing processor failure, and existing frequency adjustment methods fail to synchronize frequency restoration with voltage restoration, affecting operation efficiency.
Innovation Solution
A frequency adjusting apparatus and method that includes a clock supplying circuit, frequency division circuit, and control circuit, which select and adjust clock signals and parameters to lower and gradually increase the output clock signal frequency based on voltage thresholds, ensuring smooth frequency restoration when the voltage returns to operation levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the clock frequency is rapidly decreased when voltage drop is detected, then power dissipation is reduced and voltage can be restored, but the frequency restoration does not match voltage restoration causing processor operation efficiency to be affected
Solution Approach 1:
The system dynamically adjusts the clock frequency in multiple stages based on voltage levels. Instead of a single rapid frequency change, the frequency adjustment is divided into multiple steps that correspond to different voltage recovery stages, making the frequency response adaptive and synchronized with voltage restoration
Solution Approach 2:
The invention changes the frequency adjustment parameter from a single-step change to a multi-step gradual change. The control circuit adjusts the clock frequency through multiple intermediate levels, where each level corresponds to a specific voltage threshold, ensuring that frequency restoration matches the voltage recovery process
2Reliability
If the clock frequency is rapidly decreased to restore voltage, then voltage recovery is achieved, but frequency restoration should match voltage restoration otherwise voltage cannot afford frequency increase or processor efficiency is affected
Solution Approach 1:
The frequency adjustment process is segmented into multiple discrete steps, each associated with a specific voltage threshold. The control circuit monitors voltage levels and transitions the clock frequency through predefined steps, ensuring that each frequency change is supported by adequate voltage levels
Solution Approach 2:
The system implements a feedback mechanism where the control circuit continuously monitors the voltage level and adjusts the clock frequency accordingly. When voltage exceeds a threshold, the control circuit triggers frequency increase; when voltage drops below a threshold, it triggers frequency decrease, creating a closed-loop control system
Data Source
AI summary
A frequency adjusting apparatus used in a processing chip operated at an operation frequency according to a power is provided that includes a clock supplying circuit, a frequency division circuit and a control circuit. The clock supplying circuit outputs one of clock signals as a supplied clock signal. The frequency division circuit performs frequency division on the supplied clock signal according to a parameter to generate an output clock signal. The control circuit determines a combination of a selected clock signal and a value of the parameter for gradually increasing the frequency of the output clock signal during the increasing of the voltage value that passes through voltage value sections, wherein when the voltage value is determined to be larger than a second threshold value and when the voltage value sections correspond to higher voltage values, the selected clock signal has a higher frequency.