Clock Frequency Stepping for Stable IC Supply Voltage Regulation
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Solution Overview
Problem
Integrated circuit supply voltage controllers struggle to maintain stable voltage during abrupt changes in load, particularly when modifying clock signal frequencies, leading to overshooting or undershooting, which can exceed operating limits and pose risks to attached devices.
Innovation Solution
A method involving a series of successive frequency divisions of the clock signal with variable division ratios to standardize frequency variations, allowing the supply voltage controller to adapt and prevent overshooting or undershooting, using a frequency divider with counter-comparators to periodically subtract pulses and adjust division ratios to maintain controlled frequency differentials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock signal frequency is modified abruptly, then the frequency change is achieved quickly, but supply voltage overshooting or undershooting occurs
Solution Approach 1:
The frequency modification process is segmented into multiple intermediate steps rather than a single abrupt change. The frequency divider applies successive divisions with different division ratios (e.g., first division by 2, then by 4, then by 8) to create intermediate frequency states, allowing the supply voltage controller to gradually adapt to each step and prevent voltage overshooting or undershooting.
2Speed
If a conventional frequency divider with division ratio of 1/2 is used, then the frequency is divided, but the frequency variation amplitude remains too large (>60 MHz) causing voltage overshoots or undershoots
Solution Approach 1:
The frequency divider employs dynamic division ratios that change over time during the frequency transition process. Instead of using a fixed division ratio of 1/2, the system adjusts the division ratio sequentially (e.g., 1/2, then 1/4, then 1/8) to create smaller, controlled frequency steps. This dynamic adjustment allows the system to maintain frequency division capability while reducing the harmful frequency variation amplitude that causes voltage instability.
3Device complexity
If the controller has low internal capacitance or no dedicated external capacitive element, then the device complexity is reduced, but the response time becomes too slow to control supply voltage during load variations
Solution Approach 1:
The system performs preliminary frequency division actions before the supply voltage controller needs to respond to load variations. By pre-segmenting the frequency change into manageable steps, the system prepares intermediate states that the controller can handle with its existing capacitance, effectively extending the controller's response capability without adding capacitive elements.
Data Source
AI summary
An embodiment method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.