Clock Gate Enable Condition Redundancy Analysis
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Solution Overview
Problem
Existing circuit design technologies face challenges in identifying and removing redundant logic based on clock gate enable conditions, particularly in complex feedback conditions, which can lead to increased power consumption and logic path complexity.
Innovation Solution
The use of a satisfiability solver to analyze clock gate enable conditions and determine redundant logic paths, replacing them with constant logic values, thereby reducing logic path depth and feedback paths through clock gating, facilitated by annotating logic with observability conditions and performing depth-first searches within the circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clock gates are used to control clock signals to clocked circuit elements, then power consumption is reduced by gating clock signals when not needed, but redundant logic paths are created that increase overall circuit complexity
Solution Approach 1:
The patent extracts and removes redundant logic paths from the circuit design that were created by clock gating operations. By identifying logic that becomes redundant when clock signals are gated to specific circuit elements, the system eliminates this unnecessary logic, thereby reducing overall circuit complexity while preserving the power-saving benefits of clock gating
Solution Approach 2:
The patent changes the state of logic paths by identifying when they transition to a redundant state due to clock gating enable conditions. By detecting these parameter changes in logic observability and removing redundant paths, the system maintains optimized power consumption without the penalty of increased complexity
2Loss of energy
If redundant logic is not removed from circuit design, then clock gating can effectively control power consumption, but the logic path depth increases which can affect signal propagation and circuit performance
Solution Approach 1:
The patent extracts redundant logic paths that increase logic depth without contributing to functional output. By removing these extracted redundant paths, the system reduces logic path depth and improves signal propagation characteristics while maintaining the power management benefits of clock gating
Solution Approach 2:
The patent performs preliminary identification and removal of redundant logic paths during the design phase before the circuit is implemented. By conducting this analysis in advance using enable conditions and observability metrics, the system prevents redundant logic from being synthesized into the final design, thereby avoiding increased logic path depth from the outset
Data Source
AI summary
Various embodiments provide for determining redundant logic in a circuit design based on one or more enable conditions of clock gates, which can be part of electronic design automation (EDA). In particular, some embodiments use one or more enable conditions (of the clock gates) with a satisfiability solver to determine redundant logic coupled to clock circuit elements gated by the clock gates.