Clock Gate Locking for Hardware IP Protection
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Solution Overview
Problem
Existing logic locking techniques for protecting hardware intellectual property (IP) are vulnerable to deobfuscation attacks, such as SAT-based attacks, and face challenges in scalability and practicality for complex system-on-chips (SoCs), particularly due to the lack of electronic design automation (EDA) tool support for asynchronous designs.
Innovation Solution
The implementation of a clock gate locking mechanism that inserts key programmable integrated clock gates (ICGs) into hardware designs, using synthesis-based and intent-based approaches to prioritize and lock clock gating elements, thereby obstructing data/control flows and making logic dysfunctional for incorrect unlocking keys, while maintaining minimal design changes and supporting commercial EDA tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic locking techniques are used to protect hardware IP, then security against piracy and tampering is improved, but vulnerability to SAT-based deobfuscation attacks increases
Solution Approach 1:
Instead of locking the data path directly, the patent inverts the approach by locking the clock signal path. Clock gating cells are inserted to control clock distribution, and the lock is applied to the clock enable signals rather than the data paths. This inversion makes SAT-based attacks ineffective because the clock control logic is structurally different from traditional data path locking.
Solution Approach 2:
The patent introduces clock gating cells as intermediary elements between the clock source and the logic elements. These intermediary cells act as mediators that can be locked independently, providing a security layer that does not directly expose the data path logic to SAT attacks while still controlling the functionality of the protected IP.
2Reliability
If asynchronous latch-based designs are used for sequential locking, then resistance to SAT attacks is improved, but design complexity and EDA tool support requirements increase significantly
Solution Approach 1:
The patent uses standard synchronous flip-flops instead of complex asynchronous latches. By using readily available, well-supported synchronous elements with simple clock gating control, the solution achieves security without the burden of asynchronous design complexity. The approach treats the clock gating mechanism as a simple, replaceable security layer rather than requiring fundamental changes to the sequential element architecture.
Solution Approach 2:
The patent changes the control parameter from asynchronous enable signals to synchronous clock enable signals. By modifying the timing and control parameters to work with standard synchronous flip-flops, the solution maintains resistance to SAT attacks while avoiding the complexities of asynchronous design. The clock gating cells use standard synchronous control mechanisms that are fully supported by commercial EDA tools.
3Reliability
If multiple key programmable ICGs are inserted into the circuit, then security resilience against deobfuscation attacks is improved, but area overhead and power consumption increase
Solution Approach 1:
The patent merges the security function with the existing clock gating infrastructure. By integrating key programmable ICGs into the normal clock distribution network, the security mechanism shares the same physical resources as the power management clock gating. This merging approach provides enhanced security resilience while minimizing additional area overhead, as the ICGs utilize existing clock tree structures and routing.
4Reliability
If clock gating is applied to logic elements, then functionality is protected for incorrect keys, but performance and area overhead are introduced
Solution Approach 1:
The patent applies preliminary clock gating control to prevent incorrect key operation from affecting circuit functionality. By pre-configuring the clock enable signals through key programmable ICGs, the system proactively blocks incorrect operations before they can impact performance. This preliminary action ensures that only correctly authenticated operations receive clock signals, protecting functionality while minimizing performance impact through targeted rather than blanket gating.
Data Source
AI summary
A method and system are directed to protecting hardware intellectual property (IP) of hardware designs. The method comprises receiving a hardware locking request comprising a register transfer level (RTL) design file, generating a circuit representation of the RTL design file, wherein the circuit representation comprises a translation of the RTL design file into one or more logic elements. The method may further comprise inserting a plurality of key programmable integrated clock gates (ICGs) into the circuit representation and generating a clock gated and locked netlist based on the insertion of the plurality of key programmable ICGs into the circuit representation.