Integrated Clock Gate Insertion for Scan-Chain Toggle Control
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Solution Overview
Problem
Scan-chain testing of integrated circuit designs often causes excessive toggling, leading to false failures and potential power issues, as the testing process may exceed the designed toggle rate and power consumption limits.
Innovation Solution
The method involves detecting integrated clock gates in the circuit, comparing their fanout with threshold and maximum register numbers, and determining if the function-enable path is timing-critical. Additional clock gates and test points are inserted to control clock tree activity and limit toggle rates within design specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan-chain testing is performed on integrated circuit design, then the design can be validated from functional and timing perspectives, but portions of the integrated circuit design may toggle at a higher rate than designed for, potentially giving rise to false failures
Solution Approach 1:
The patent divides the clock tree into multiple segments by inserting integrated clock gates at strategic locations. Each clock gate controls a specific segment of the clock tree, allowing independent control of clock distribution to different parts of the circuit during testing. This segmentation enables selective clocking of only those segments necessary for the current test, thereby reducing overall toggling activity while maintaining test validity.
Solution Approach 2:
The patent performs preliminary analysis of the test pattern to determine which clock gates need to be enabled before actual testing begins. By pre-configuring the clock gate states based on the known test sequence, the system can prevent unnecessary toggling from the outset while ensuring that required functional blocks are properly clocked during their active test periods.
2Reliability
If testing is performed to validate the integrated circuit design, then functional and timing perspectives can be checked, but power consumption may exceed designed limits due to higher toggle rates
Solution Approach 1:
The clock tree is segmented into controllable regions using integrated clock gates, allowing the testing system to activate only the specific segments required for each test case. This selective activation significantly reduces the total number of toggling elements during testing, thereby lowering dynamic power consumption while still achieving comprehensive design validation.
Solution Approach 2:
The patent implements periodic control of clock gates based on the test sequence requirements. Clock gates are enabled only during the specific time periods when their associated functional blocks need to be tested, and disabled during idle periods. This periodic activation pattern reduces average power consumption compared to continuous clocking of the entire circuit during testing.
Data Source
AI summary
A method of testing an integrated circuit device includes detecting a number of integrated clock gates (ICGs) in the device. Each ICG can stop clock propagation in a respective branch of a clock tree of the device. For each detected ICG, an ICG fanout (a number of digital inputs that the output of each ICG can feed) is compared with a threshold number of registers. When the ICG fanout is greater than the threshold number, it is determined whether a function-enable path of an existing ICG is timing-critical. When the function-enable path of the existing ICG is timing-critical, an additional ICG and a test point are inserted into the device as a clock input to the existing ICG. When the function-enable path of the existing ICG is not timing-critical, a test point and an AND-gate may be inserted in that function-enable path.