Clock-Gated Chien Search for Low-Power Error Correction Decoding
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Solution Overview
Problem
Conventional flash memory technologies face challenges in reducing power consumption during error correction decoding processes, particularly in Chien search algorithms, which can lead to increased energy usage and heat generation.
Innovation Solution
Implementing a clock-gating scheme in error correction decoders that dynamically deactivates functional units based on the rank of the error locator polynomial, using a power saving unit to control clocks and selectively deactivate subsets of functional units that compute terms with degrees exceeding the current error correction capability, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all functional units are activated during Chien search, then decoding accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the activation state of functional units variable rather than fixed. The clock-gating mechanism dynamically enables or disables functional units based on the actual error rank detected during decoding, allowing the system to adapt its power consumption to the actual workload while maintaining decoding accuracy when errors are present
Solution Approach 2:
The patent changes the operational parameter of functional units from a static 'always on' state to a dynamic state controlled by clock-gating signals. By modifying the clock signal parameters (enabling/disabling clock cycles) to functional units based on error rank, the system achieves power savings without compromising the reliability of error correction
2Use of energy by moving object
If functional units are deactivated to save power, then energy consumption reduces, but decoding capability may be compromised
Solution Approach 1:
The patent implements partial action by activating only the necessary number of functional units corresponding to the actual error rank. Instead of always activating all functional units (excessive action), the system activates exactly the number needed for the current error condition, achieving power savings while maintaining sufficient decoding capability
Solution Approach 2:
The patent uses feedback from the error detection stage to control the activation of functional units. The error rank information feeds back to the clock-gating mechanism, which then adjusts the activation state of functional units accordingly, ensuring that decoding capability is maintained at the appropriate level for the actual error conditions
3Reliability
If maximum error correction capability is designed, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the functional units into groups that can be independently controlled via clock-gating. By dividing the functional units and their associated clock signals into manageable segments, the system can activate only the necessary segments based on error rank, reducing the effective complexity for any given decoding operation while maintaining the capability to handle maximum errors when needed
Data Source
AI summary
Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the apparatus comprising a sequence of functional units each operative to compute a corresponding term in the sequence of terms included in the error locator polynomial, each term having a degree; and a power saving unit operative to de-activate at least one individual functional unit from among the sequence of functional units, the individual functional unit being operative, when active, to compute a term whose degree exceeds the rank.