Clock-Gated Counter Circuit for Lower Power High-Bit Counting
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Solution Overview
Problem
Existing counter circuits for mobile devices face increased power consumption due to all flip-flops receiving the same clock signal, regardless of their operation probability, leading to inefficiency in processing higher-bit counts.
Innovation Solution
A counter circuit design that includes a first counter for lower bits, a second counter for higher bits, and a clock transmission control circuit to selectively supply the clock signal to the higher-bit counter based on the carry-out signal from the lower-bit counter, reducing the input clock operation ratio and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all flip-flops receive the same clock signal to ensure uniform operation control, then the circuit structure is simple and easy to implement, but power consumption increases because all flip-flops operate at the same rate regardless of their operation probability
Solution Approach 1:
The counter circuit is divided into a lower-bit counter and a higher-bit counter, with the higher-bit counter further segmented into multiple groups. Each group receives clock signals selectively based on the operation state of the lower-bit counter, allowing different parts of the circuit to operate at different rates and reducing overall power consumption.
Solution Approach 2:
The clock signal transmission to the higher-bit counter is made dynamic rather than static. The clock transmission control circuit adjusts whether clock signals are supplied to different groups of the higher-bit counter based on the carry-out signals from the lower-bit counter, enabling the circuit to adapt its operation rate to actual computational needs.
2Stability of the object's composition
If the higher-bit counter operates at the same clock rate as the lower-bit counter to maintain consistent timing, then timing synchronization is simple, but the operation probability mismatch causes unnecessary power consumption in the higher-bit counter
Solution Approach 1:
The higher-bit counter groups receive clock signals periodically based on the operation of the lower-bit counter. When the lower-bit counter completes a full cycle (generates a carry-out signal), the corresponding higher-bit counter group receives a clock signal to update its state, creating a periodic rather than continuous operation pattern that reduces power consumption.
Solution Approach 2:
The clock transmission control circuit acts as an intermediary between the lower-bit counter and the higher-bit counter groups. It receives carry-out signals from the lower-bit counter and conditionally transmits clock signals to the higher-bit counter groups, mediating the timing relationship and enabling asynchronous operation rates while maintaining eventual synchronization.
3Use of energy by moving object
If clock gating is applied to stop clock input to reduce power consumption, then power saving is achieved, but the circuit cannot stop clock input when the enable signal is always high, limiting its effectiveness
Solution Approach 1:
The higher-bit counter is segmented into multiple groups, each with independent clock transmission control. This segmentation allows different groups to receive clock signals at different rates or be completely disabled based on their specific operational needs, providing finer-grained control flexibility beyond a single global enable signal.
Solution Approach 2:
Different groups of the higher-bit counter receive different clock signal treatments based on their local operational requirements. The clock transmission control circuit applies different control logic to different groups, allowing some groups to operate while others are disabled, creating local quality variations in clock signal supply that optimize power consumption for each specific counter group.
Data Source
AI summary
A counter circuit adding a first value indicated by a plurality of bits and a second value in response to a clock signal, a first part of the plurality of bits being lower order than a second part of the plurality of bits, the counter circuit including a first counter configured to add the first part of the plurality of bits and the second value in response to the clock signal to output a third value regarding a result of adding the first and the second values, a second counter configured to add the second part of the plurality of bits and a fourth value in response to the clock signal, and a clock transmission control circuit coupled to the first and second counters to receive the clock signal and the third value, and to control whether or not to supply the clock signal to the second counter in accordance with the received third value.