Clock-Gated Time-Borrowing Flip-Flop for Hold Time Stability

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Solution Overview

Problem

Time borrowing flip-flops in microprocessors face challenges with sequential hold time degradation at lower voltages, leading to frequency-independent functional failures, particularly in min-delay paths, which require additional buffer insertion and result in area and routing overhead.

Innovation Solution

The implementation of a clock gated scan multiplexer time borrowing flip-flop circuit that maintains the hold time equivalent to non-time borrowing flip-flops, reducing setup time by 0.8FO4/1.0FO4 while eliminating the need for min-delay buffers, thereby addressing hold time violations and improving circuit performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If clock inverters are inserted between master and slave latches to create time borrowing window, then operating frequency is improved, but hold time deteriorates requiring additional buffers

Engineering Contradiction:

Improveoperating frequencyVSAvoidhold time

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing complement values in lookup tables before they are needed. The complement values are generated in advance and stored, so when the time borrowing flip-flop needs to maintain hold time, the pre-stored values are immediately available without requiring additional buffer insertion, thus resolving the hold time deterioration issue while maintaining frequency improvement

Inventive Principle:

Principle #10Preliminary action

2Reliability

If min delay buffer insertion is used to fix hold time violations, then hold time is improved, but area and routing overhead increase

Engineering Contradiction:

Improvehold timeVSAvoidarea overhead

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent uses copying by creating complement values (inverted versions of original values) and storing them in lookup tables. Instead of inserting physical buffer circuits to fix hold time violations, the invention copies the necessary data in complement form and makes it available through the time borrowing mechanism, thereby maintaining hold time without the area and routing overhead of additional buffers

Inventive Principle:

Principle #26Copying

3Speed

If master latch is delayed to create time borrowing window, then frequency is improved, but setup time increases

Engineering Contradiction:

Improveoperating frequencyVSAvoidsetup time

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent applies parameter changes by utilizing complement values (inverted logic states) to alter the timing characteristics of the flip-flop. By switching between original and complement values stored in lookup tables, the invention changes the effective setup time parameter, allowing the master latch delay to be compensated without increasing the apparent setup time, thus maintaining both frequency improvement and acceptable setup time

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10382019B2Time borrowing flip-flop with clock gating scan multiplexer

Publication Date: 2019.08.13 INTEL CORP

AI summary

An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain of at least four inverters one of which has an input to receive the clock.