Clock-Gated Reset Synchronization for Multi-Flip-Flop Circuits
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Solution Overview
Problem
Existing reset methods for digital circuits face issues with asynchronous signal timing violations and propagation delays, leading to errors in flip-flop outputs, which are typically addressed by increasing the number of buffers, thereby increasing circuit size and cost.
Innovation Solution
A method involving a clock controller and a reset signal control unit that generates and synchronizes clock and reset signals, keeping the clock signal at a logic level during reset operations to prevent timing errors and propagation delays across multiple flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extra buffers are used to balance propagation delay, then reset signal synchronization is improved, but circuit size and cost increase
Solution Approach 1:
The clock controller pauses the clock signal before the reset signal is applied to the flip-flops, and maintains it paused during the reset operation. This preliminary action ensures that all flip-flops receive the reset signal simultaneously without requiring propagation delay compensation buffers, thereby reducing circuit complexity while maintaining reset synchronization reliability
2Speed
If reset signal is transmitted to multiple flip-flops simultaneously, then reset operation speed is improved, but timing errors occur due to propagation delay
Solution Approach 1:
The system pauses the clock signal in advance before applying the reset signal to multiple flip-flops. This preliminary pausing action creates a time window during which all flip-flops can be reset simultaneously without timing errors, achieving both fast reset operation and precise timing accuracy without requiring slow sequential resetting
3Productivity
If clock signal continues during reset operation, then system productivity is maintained, but timing violations occur at flip-flop outputs
Solution Approach 1:
The clock controller pauses the clock signal immediately before the reset operation begins and maintains the pause throughout the reset duration. This preliminary and sustained pausing prevents timing violations at flip-flop outputs while minimizing interruption to system productivity by resuming the clock signal immediately after reset completion
Data Source
AI summary
The present invention discloses a reset method for a digital circuit. The method includes: providing a clock signal to the digital circuit; keeping the clock signal at a logic level according to a first indicating signal; generating a reset signal for resetting the digital circuit; and recovering the clock signal to the digital circuit according to a second indicating signal.