Clock-Gated Storage Element for Probe-Induced Hold-Time Protection
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Solution Overview
Problem
WRITE ENABLE signals are vulnerable to probing attacks, particularly in scenarios involving multi-bit custom registers and address bit combinations that reveal cryptographic key bits, making them preferred targets for attackers.
Innovation Solution
A storage element with a clock gating circuitry that generates gated clock signals using small capacitance connections, incorporating tri-state circuitry like C2MOS or transmission gate circuitry, and Boolean circuitry based on input signals, to create a hold-time violation when probed, thereby increasing security against such attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock gating circuitry with larger capacitance connections is used, then the wiring effort is reduced and manufacturing is easier, but the circuit becomes vulnerable to probing attacks that can read or reconstruct cryptographic information
Solution Approach 1:
The patent changes the capacitance parameter of the clock gating circuitry connections from conventional larger values to specifically small values (below 10 fF, preferably below 1 fF). This parameter change creates hold-time violations when probing is attempted, as the small capacitance cannot maintain the signal state during the attack, thereby preventing successful information extraction while maintaining manufacturing feasibility
Solution Approach 2:
The patent converts the typically harmful effect of capacitance (which can cause signal degradation) into a beneficial security feature. By designing the clock gating circuitry with intentionally small capacitance values, any probing attempt that introduces additional capacitance will cause hold-time violations and disrupt the attack, thus converting the physical property of capacitance from a potential weakness into an active defense mechanism
2Reliability
If standard physical connections with larger capacitance are used in clock gating circuitry, then signal stability is maintained, but the circuit is susceptible to probing attacks that can observe address-gated clock signals
Solution Approach 1:
The patent specifies precise capacitance parameter ranges for the clock gating circuitry connections (below 10 fF, preferably below 1 fF). This requires manufacturing processes capable of controlling connection capacitance at very low levels, but the benefit is that the small capacitance value itself becomes the security mechanism that prevents successful probing attacks by causing hold-time violations
Solution Approach 2:
The small capacitance connections act as an intermediary defense mechanism between the cryptographic operations and potential probing attacks. The capacitance value serves as a physical barrier that disrupts any attempt to tap into the clock signals, as the introduced probing capacitance will cause hold-time violations that prevent successful signal observation
Data Source
AI summary
A storage element that is operable based on a system clock signal, the storage element including a clock gating circuitry configured to generate a gated clock signal based on at least one Boolean signal and the system clock signal or a preprocessed system clock signal, wherein the clock gating circuitry comprises physical connections of small capacitance such that tapping of at least one of the physical connections results in a hold-time violation. Also, a hardware-based cryptography accelerator or a secured processing system including at least one such storage element, and a method for operating at least one storage element.