Clock Gater Latch Structure With Adjustable Reset Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock gater latch structures in synchronous circuits face challenges in efficiently managing clock signals to reduce dynamic power dissipation, as they often require additional logic gates in critical timing paths, which can introduce delays and increase power consumption.
Innovation Solution
The integration of latch circuits with at least two transistors configured to perform NAND or NOR functions, controlled by a second clock signal, allows for adjustable timing of the clock signal's passing to the output, enabling early or late resets based on an enable signal, thereby optimizing power management without additional gates in the critical timing path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If additional logic gates are added to the critical timing path to achieve clock gating, then power dissipation is reduced, but timing delays increase and power consumption increases
Solution Approach 1:
The patent merges the clock gating function with the latch circuit structure itself, eliminating the need for separate logic gates in the critical timing path. The latch circuit integrates clock gating transistors that directly control clock signal propagation to flip-flops, combining storage and clock gating functions in a single unified structure.
Solution Approach 2:
The patent extracts the clock gating functionality from traditional logic gate implementations and relocates it directly into the latch circuit's clock path. By placing clock gating transistors within the latch structure, the design removes unnecessary intermediate logic gates that were previously required to achieve clock gating, thereby reducing timing delays while maintaining power savings.
2Loss of energy
If clock gating is implemented to reduce dynamic power dissipation, then switching power consumption decreases to zero, but additional logic is required in the circuit
Solution Approach 1:
The patent combines clock gating transistors with the latch circuit structure, merging two previously separate functions (latch operation and clock gating) into a single integrated unit. This integration eliminates the need for additional standalone logic gates, reducing device complexity while maintaining the power consumption benefits of clock gating.
Solution Approach 2:
The latch circuit is designed to perform multiple functions simultaneously: it acts as both a storage element and a clock gating mechanism. The clock gating transistors within the latch structure enable the circuit to control clock signal propagation while maintaining its primary latch functionality, thereby achieving multi-functionality without increasing overall circuit complexity.
3Productivity
If transistors are added to alter clock signal timing, then power management is optimized, but device complexity increases
Solution Approach 1:
The patent merges clock gating transistors with the existing latch circuit structure, so that the transistors serve dual purposes: maintaining latch functionality and enabling clock signal timing control. This integration ensures that the transistor count increase is minimized, as the same transistors perform multiple functions rather than requiring separate dedicated components.
Solution Approach 2:
The latch circuit incorporates dynamically controllable clock gating transistors that can adjust their operation based on control signals. This dynamic behavior allows the circuit to optimize power management by enabling or disabling clock signal propagation as needed, while the transistors remain part of the integrated latch structure, preventing excessive complexity increase.
Data Source
AI summary
According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state of an enable signal, substantially pass the first clock signal to an output signal. The latch circuit may include at least two transistors configured to essentially perform a NAND function and controlled by a second clock signal, wherein the at least two transistors are configured to alter the timing of the substantial passing of the first clock signal to the output signal.