Clock Gating Abstraction Refinement for Power Reduction
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Solution Overview
Problem
Reducing power consumption in electronic chip designs while ensuring correct behavior and automatically determining clock gating functions to achieve this reduction.
Innovation Solution
Implementing a computerized system that modifies circuit designs by introducing a clock gating function, using a model checker to determine equivalence between original and gated circuit designs, and iteratively refining the clock gating function based on counter-examples to maintain correct behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock gating function is introduced to reduce power consumption, then energy efficiency is improved, but circuit correctness may be compromised
Solution Approach 1:
The system uses model checking to verify circuit correctness and provides feedback to refine the clock gating function. The equivalence checker compares the original circuit with the clock-gated circuit, and if discrepancies are found, the clock gating function is adjusted accordingly to maintain correctness while achieving power reduction.
Solution Approach 2:
The system performs preliminary equivalence checking and model validation before finalizing the clock gating function. By预先 verifying circuit correctness through model checking and equivalence comparison, the system ensures that power reduction measures do not compromise circuit functionality.
2Reliability
If model checking is used to verify equivalence, then circuit correctness is ensured, but computational complexity increases
Solution Approach 1:
The verification process is divided into separate modules: equivalence checking, model checking, and refinement. Each module handles a specific aspect of the verification, making the overall complex process more manageable and efficient by breaking it down into smaller, specialized tasks.
Solution Approach 2:
The system introduces an equivalence checker as an intermediary between the circuit design and model checking processes. This intermediary component simplifies the verification by first checking for obvious equivalences before invoking more complex model checking, thereby reducing overall computational complexity.
3Reliability
If iterative refinement is performed to maintain equivalence, then circuit correctness is maintained, but design time increases
Solution Approach 1:
The system performs preliminary equivalence checking using simpler methods before iterative refinement. By预先 identifying obvious equivalences and potential issues, the system reduces the number of iterative refinement cycles needed, thereby maintaining correctness while minimizing additional design time.
Solution Approach 2:
The iterative refinement process automatically adjusts the clock gating function based on model checking results without requiring manual intervention. The system self-corrects equivalence violations by automatically refining the gating logic, which maintains correctness while reducing the time overhead compared to manual verification and adjustment.
Data Source
AI summary
An initial clock gating function is introduced to an original circuit design. Using abstraction-refinement, the initial clock gating function is modified such that the gated circuit design is equivalent to the original circuit design. A model checker, such as a SAT solver, may be utilized to determine equivalency of two circuit designs. A counter-example may be determined by the model checker to negate equivalency. The counter-example may be utilized to modify the initial clock gating function to determine a modified gated circuit design that is equivalent to the original circuit design.