Clock Gating Circuitry with Adjustable Delay for Power Optimization
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Solution Overview
Problem
Conventional clock gating methods in synchronous circuitry often result in unnecessary power consumption due to early clock reactivation, as they are designed to account for worst-case propagation delays, leading to power wastage in scenarios with better-than-worst-case propagation times or lower frequencies.
Innovation Solution
A clock signal control circuitry that stores a delay value, allowing for adjustable delays in clock switching between modes, ensuring the clock is activated only when necessary, thereby optimizing power savings while maintaining system robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock is reactivated early to account for worst-case propagation delays, then system reliability is improved, but power consumption increases due to unnecessary clock cycles
Solution Approach 1:
The patent implements dynamic clock gating control by adjusting the gating signal timing based on actual propagation delay measurements. Instead of using fixed worst-case delays, the system dynamically adapts the clock gating timing to match the real-time propagation characteristics of the clock tree, thereby eliminating unnecessary clock cycles while ensuring the module is ready when the clock is reactivated.
Solution Approach 2:
The system changes the timing parameter of the clock gating signal based on measured propagation delays. By measuring the actual propagation delay through the clock tree and adjusting the gating signal accordingly, the system optimizes the balance between reliability and power consumption, avoiding the energy waste associated with fixed worst-case timing margins.
2Reliability
If the clock gating control uses fixed worst-case delay values, then system robustness is improved, but power efficiency deteriorates due to unnecessary clock activation
Solution Approach 1:
The patent implements a feedback mechanism where the system measures the actual propagation delay through the clock tree and uses this measured value to adjust the clock gating timing. This closed-loop approach replaces fixed worst-case assumptions with real-time feedback, enabling the system to achieve both robustness and power efficiency by adapting to actual operating conditions.
Solution Approach 2:
The system performs preliminary measurement of propagation delays during initialization or calibration phases, storing these measured values for use during normal operation. This preliminary action allows the system to operate with optimized timing parameters rather than conservative worst-case values, improving power efficiency while maintaining reliability.
3Productivity
If the clock tree depth is increased to improve system performance, then processing capability is improved, but propagation delay increases causing greater latency
Solution Approach 1:
The system performs preliminary measurement of the clock tree propagation delay during initialization, allowing it to know the exact delay characteristics of its clock distribution network. This information is then used to optimize the clock gating timing, compensating for the propagation delay without requiring excessive early reactivation of the clock.
Data Source
AI summary
Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal. It comprises: an input for receiving mode switching signals indicating said synchronous circuitry is to switch between modes, said mode switching signals comprising a clock gating request signal indicating said synchronous circuitry is to enter a sleep mode during which said circuitry is not clocked and a wake up request signal indicating said synchronous circuitry is to enter an operational mode during which said circuitry is clocked; and is responsive to said clock gating request signal to gate said clock signal such that no clock signal is output to said synchronous circuitry and being responsive to said wake up request signal to output said clock signal to said synchronous circuitry. The clock signal control circuitry further comprises: a data store for storing a delay value; and delay circuitry for delaying switching of said clock signal between modes in response to at least one of said mode switching signals, said delay circuitry delaying said switching by an amount dependent upon said stored delay value.