Clock Gating Buffer Circuit With Lower Transistor Count
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Solution Overview
Problem
Existing clock gating circuits in computing devices consume power even when components are not in use, leading to inefficiency and increased power consumption, and high-performance circuits require more components, increasing area overhead.
Innovation Solution
A high-performance clock gating circuit design using a combination of p-channel and n-channel transistors, inverters, and tristate inverters to selectively enable or disable the local clock signal based on control signals, reducing power consumption and component count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional clock gating circuits are used to disable clock signals when components are idle, then power consumption is reduced, but the circuits still consume some power and require multiple transistors increasing area overhead
Solution Approach 1:
The patent combines the clock gating function with the existing clock buffer structure by integrating control transistors directly into the buffer circuit. This merging eliminates the need for separate gating circuits, reducing the total transistor count from traditional designs that require 4-6 transistors per gate to this design that achieves the same function with fewer transistors by sharing components between the buffer and gating functions.
Solution Approach 2:
The clock buffer circuit is designed to perform multiple functions: it acts as both a clock buffer (signal amplification and distribution) and a clock gate (conditional blocking). By making the buffer multi-functional, the patent eliminates the need for dedicated gating transistors, thereby reducing area overhead while maintaining the ability to disable clock signals during idle periods for power savings.
2Reliability
If more transistors are used in clock gating circuits to improve performance, then clock signal control is enhanced, but area overhead increases
Solution Approach 1:
The patent merges the clock gating control mechanism with the clock buffer structure by integrating control transistors into the buffer circuit paths. This integration maintains reliable clock signal control through the buffer's inherent signal driving capability while avoiding the area overhead of separate gating circuits, achieving both reliable control and compact design.
Solution Approach 2:
The clock buffer is segmented into multiple paths with individual control transistors that can independently block clock signals to different outputs. This segmentation allows precise control of clock distribution while using a compact structure that minimizes area overhead compared to traditional approaches that require separate gating circuits for each output path.
Data Source
AI summary
Methods, apparatus, and systems are described to perform clock gating. An example apparatus to perform clock gating includes a first transistor; a second transistor including a first terminal and a second terminal, the first terminal of the second transistor coupled to a first terminal of the first transistor, the second terminal of the second transistor coupled to a second terminal of the first transistor; an inverter including an input terminal coupled to the first terminal of the first transistor and the first terminal of the second transistor; and a tristate inverter including an input terminal and an output terminal, the input terminal of the tristate inverter coupled to an output terminal of the inverter, the output terminal of the tristate inverter coupled to the input terminal of the inverter, the first terminal of the first transistor, and the first terminal of the second transistor.