Clock Gating Unit for Bus Bridge Power Reduction
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Solution Overview
Problem
System-on-chip (SoC) devices face high power consumption due to continuous clocking in bus bridge devices, even when they are idle, leading to increased energy expenditure and heat generation, which can cause malfunctions and package damage.
Innovation Solution
Implementing a clock gating unit that detects transaction states on the bus system, using a dynamic clock gate and clock gating cell to selectively suspend or provide the clock signal to the bus bridge device, thereby reducing power consumption by gating the root clock based on transaction detection signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous clocking is applied to bus bridge devices, then system performance and responsiveness are maintained, but power consumption increases and heat generation occurs
Solution Approach 1:
The patent implements periodic clock gating by monitoring transaction states and selectively enabling/disabling the clock signal to the bus bridge device. The clock is provided only during active transaction periods and gated off during idle periods, transforming continuous clocking into periodic clocking to reduce power consumption while maintaining system performance when needed.
2Reliability
If continuous clocking is applied to bus bridge devices, then operational readiness is maintained, but heat generation increases causing malfunctions and package damage
Solution Approach 1:
The clock gating unit periodically activates the clock signal based on transaction detection, ensuring the bus bridge device is ready to operate when transactions occur while minimizing active clocking duration. This periodic operation reduces cumulative heat generation that would occur with continuous clocking, preventing thermal malfunctions and package damage.
3Use of energy by moving object
If clock gating is implemented to reduce power consumption, then energy efficiency improves, but system complexity increases
Solution Approach 1:
The patent introduces a clock gating unit as an intermediary component between the clock source and the bus bridge device. This intermediary monitors transaction states and controls clock signal delivery, adding minimal complexity while achieving significant energy efficiency improvements. The clock gating unit acts as a mediator that enables selective clocking without fundamentally redesigning the entire bus system.
4Speed
If clock signal is continuously provided, then transaction processing speed is maintained, but energy waste occurs during idle periods
Solution Approach 1:
The system implements periodic clock signal provision by detecting transaction states and enabling the clock only during active transaction periods. During idle periods, the clock is gated off to eliminate energy waste. When transactions occur, the clock is re-enabled to maintain transaction processing speed, achieving a balance between speed and energy efficiency through periodic operation.
Data Source
AI summary
A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.