Clock Gating Cell Control for Transition Delay Fault Testing
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Solution Overview
Problem
The complexity of testing for Transition Delay Faults (TDFs) in modern integrated circuits is exacerbated by the use of layers of clock gating logic, making it difficult to generate pseudorandom data capable of capturing all TDFs, as the probability of capturing faults decreases exponentially with each additional gating cell, rendering existing methods ineffective.
Innovation Solution
Decoupling the TE pins of clock gating cells from other circuit elements and controlling them with a unique signal, known as CLK_UNGATE, allows independent control of the clock gating logic during test mode, ensuring the presence of the two clock pulses needed to capture TDFs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clock gating logic is used to decrease power consumption, then power consumption is reduced, but the complexity of testing for TDFs increases and the probability of capturing faults decreases exponentially
Solution Approach 1:
The patent segments the control of clock gating cells by separating the test mode control signal (TEST_SE) from the clock gating control. By introducing a dedicated control mechanism for clock gating cells during scan testing, the system can independently manage the clock gating function without being constrained by the pseudorandom data generation process, thereby maintaining power savings while improving testability
Solution Approach 2:
The patent introduces an intermediary control signal (CLK_UNGATE) that mediates between the test mode and the clock gating function. This intermediary signal allows the tester to independently control the clock gating cells during scan testing, ensuring that clock pulses are available for TDF detection while maintaining the power consumption benefits of clock gating in normal operation
2Loss of energy
If layers of clock gating logic are added to modern circuits, then power consumption decreases, but the probability of capturing all TDFs with pseudorandom data becomes exponentially smaller
Solution Approach 1:
The patent makes the clock gating control dynamic by allowing independent control during test mode. The CLK_UNGATE signal can be dynamically adjusted based on the testing requirements, enabling the system to transition between power-saving mode and test-mode independently, thereby ensuring reliable TDF detection regardless of the number of clock gating layers
Solution Approach 2:
The patent changes the control parameter for clock gating cells from being driven by pseudorandom data to being driven by a dedicated test control signal. This parameter change ensures that clock pulses are reliably generated for TDF detection while maintaining the ability to save power during normal operation through conventional clock gating control
3Adaptability or versatility
If the TE pins of clock gating cells are coupled to TEST_SE signal, then the circuit operates as a single integrated system, but the tester cannot independently control clock gating during scan testing
Solution Approach 1:
The patent segments the control function by separating the TEST_SE signal path from the clock gating control path. By introducing a dedicated CLK_UNGATE signal for clock gating cell control during scan testing, the system maintains integrated operation during normal function while enabling independent control during testing, thus resolving the contradiction between system integration and testing flexibility
Solution Approach 2:
The patent introduces CLK_UNGATE as an intermediary control signal that provides independent control of clock gating cells during scan testing. This intermediary signal allows the tester to control clock gating independently without affecting the normal integrated operation of the circuit, thereby maintaining both system integration and testing flexibility
Data Source
AI summary
A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.