Clock Gating Cell for Structural Delay-Fault Test Coverage
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Solution Overview
Problem
Structural at-speed delay-fault tests in integrated circuits face low test coverage due to uncontrollable or partially controllable logics, leading to inaccurate tests and elevated power consumption, as existing technologies struggle to maintain a controllable clock signal during capture cycles in scan circuits.
Innovation Solution
A method and clock gating cell design that output a controllable waveform of a clock signal during capture cycles, eliminating partially enabled clock signals by using clock gating cells with additional control signals like shift-enable and delay-test-enable, allowing for precise control of clock signals and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock gating cells are used in scan circuits during structural delay-fault tests, then the circuit structure remains simple, but the clock signals become uncontrollable or partially controllable during capture cycles, leading to low test coverage
Solution Approach 1:
The clock gating cell is segmented into multiple independent control inputs (scan-enable, delay-test-enable, functional-enable) that can independently control the clock signal path. This segmentation allows different portions of the circuit to be controlled differently during test operations, enabling full controllability of clock signals during capture cycles while maintaining simple functional operation during normal mode.
Solution Approach 2:
The clock gating cell implements dynamic control by allowing the enable signals to change the clock signal path based on operational mode. During scan test capture cycles, the delay-test-enable signal can dynamically control whether the clock signal is gated or passed through, enabling adaptive control of clock distribution to achieve complete test coverage while maintaining simplicity in functional mode.
2Reliability
If clock signals are continuously provided during capture cycles to maintain signal controllability, then test coverage is improved, but power consumption increases due to unnecessary clock switching in non-scan elements
Solution Approach 1:
The clock gating cell applies local quality control by enabling clock signals only in specific regions where scan elements are present. The enable signals allow selective activation of clock distribution to only those circuit portions requiring test operations, while keeping clock gating active in other regions to prevent unnecessary switching and reduce power consumption during capture cycles.
3Reliability
If additional control signals are added to clock gating cells to achieve full controllability during test operations, then test coverage and accuracy are improved, but the device complexity and control logic increase
Solution Approach 1:
The clock gating cell is designed with multi-functionality to handle both functional operation and various test operations (scan shift, scan capture, delay testing) through a unified structure. The additional control signals (scan-enable, delay-test-enable, functional-enable) are integrated into the existing clock gating cell architecture, allowing it to perform multiple functions without requiring separate control circuits for each operation mode.
Data Source
AI summary
Methods and devices applying to a clock system of scan circuits to enhance the test coverage for structural delay-fault tests are provided. According to an aspect, a method applying to a clock system of a scan circuit of a scan test containing one or more clock gating cells includes at any stage of the scan test outputting a controllable waveform of a clock signal at each clock gating cell, and eliminating a partially enabled clock signal during a capture cycle at each clock gating cell.