Clock Gating Cell Relocation for Power Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Clock gating in clock trees of portable devices often fails to effectively turn off unused areas, leading to unnecessary power consumption due to the proximity of clock gating cells to logic gates.
Innovation Solution
The method involves determining a timing margin for paths between clock gating cells and digital data storage elements, moving the clock gating cells closer to the clock source when the timing margin meets a threshold, and inserting buffers to reduce clock phase delay and deviations, thereby allowing more areas of the clock tree to be turned off when not in use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the clock gating cell is located close to the logic gates, then the enable signal can be effectively transmitted to the logic gates, but the clock gating cell cannot turn off certain areas of the clock tree that are not in use, resulting in increased power consumption
Solution Approach 1:
The patent introduces an intermediary mechanism (timing margin analysis and automatic relocation system) that mediates between the clock gating cell and the logic gates. The system calculates timing margins and automatically relocates the clock gating cell to an optimal position that balances enable signal effectiveness with power conservation, allowing the cell to be positioned farther from logic gates while maintaining functional reliability.
Solution Approach 2:
The patent changes the positional parameter of the clock gating cell based on timing margin calculations. By dynamically adjusting the location parameter of the clock gating cell relative to the logic gates and clock source, the system optimizes both power consumption and enable signal effectiveness, resolving the contradiction between proximity requirements and power savings.
2Loss of energy
If the clock gating cell is moved closer to the clock source, then more areas of the clock tree can be turned off to conserve power, but the timing margin for the enable signal to reach the digital data storage element may be compromised
Solution Approach 1:
The patent performs preliminary timing margin analysis before finalizing the clock gating cell position. The system calculates the timing margin for the enable signal path in advance, ensuring that moving the clock gating cell closer to the clock source will not compromise the timing requirements for digital data storage elements. This preliminary verification allows aggressive power optimization while maintaining timing integrity.
3Reliability
If buffers are inserted to reduce clock phase delay and deviations, then delay uncertainty is reduced and correct data latching is ensured, but the device complexity increases
Solution Approach 1:
The patent applies buffers selectively rather than uniformly throughout the clock tree. The system identifies specific paths where clock phase delay and deviations exceed thresholds, and inserts buffers only in those localized areas. This selective approach reduces delay uncertainty and ensures correct data latching while minimizing the overall increase in device complexity by avoiding unnecessary buffer insertions.
Data Source
AI summary
In a particular embodiment, a method of generating an advanced gating cell clock tree includes determining a timing margin for a path between a clock gating cell and a digital data storage element such as a latch or flip flop. The circuit contains a clock source and when the timing margin for the path meets a predetermined threshold, the clock gating cell is automatically moved closer to the clock source. In a particular embodiment, the timing margin is automatically determined. A clock tree synthesis is performed to insert one or more buffers into the path and create an advanced gating cell clock tree.