Automated Clock Gating Circuit Generation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Manual clock gating in ASIC and FPGA designs is complex and time-consuming, requiring intimate knowledge of the design, and often introduces errors due to the need for manual addition of gating logic, especially when dealing with legacy and third-party IP design cores.
Innovation Solution
A method for generating clock gating circuitry that involves determining Boolean expressions of observability conditions for interconnected gate elements, which are then used to create clock gating circuits, allowing for automated and efficient reduction of power consumption by dynamically enabling and disabling circuit elements based on observability and toggle conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If manual clock gating logic is added to ASIC and FPGA designs, then power consumption is reduced, but design complexity and time requirements increase
Solution Approach 1:
The system performs self-service by automatically generating clock gating logic through software that analyzes the circuit design model, netlist, and timing constraints to produce optimized gating signals without requiring manual designer intervention for each gating decision
Solution Approach 2:
The manual mechanical process of adding clock gating logic is replaced by an automated software-based system that uses algorithms to analyze circuit behavior, determine observability conditions, and generate gating logic automatically
2Loss of energy
If manual clock gating logic is added to legacy and third-party IP design cores, then power consumption is reduced, but error introduction risk increases
Solution Approach 1:
The system uses feedback by continuously analyzing the circuit design model, netlist, and timing constraints to verify that generated clock gating logic maintains correct circuit operation and does not introduce errors, especially important when dealing with legacy and third-party IP cores
Solution Approach 2:
The software acts as an intermediary between the legacy/third-party IP design cores and the clock gating implementation, automatically analyzing and generating appropriate gating logic without requiring direct manual modification of potentially proprietary or legacy code
3Productivity
If automated software is used to generate clock gating logic, then productivity increases, but computational complexity increases
Solution Approach 1:
The software divides the complex task of clock gating generation into manageable segments by analyzing the circuit design model, netlist, and timing constraints separately, then integrating the results to produce the final gating logic
Solution Approach 2:
The system changes parameters by accepting different input formats (circuit design model, netlist, timing constraints) and transforming them into optimized clock gating logic, adapting to various design scenarios and constraints
Data Source
AI summary
In one embodiment, a method is provided for generating clock gating circuitry for a circuit design model. A Boolean expression of path sensitization is determined for each gate element in the netlist of a circuit design. For each gate element, a conjunction of the Boolean expression of the path sensitization and a Boolean expression of a disjunction of the observability conditions of one or more subsequent gates is determined to produce an intermediate Boolean expression. Intermediate Boolean expressions are backward retimed to produce the respective Boolean expression of the observability conditions of the each gate element. Clock gating circuits that implement the respective Boolean expression of the observability conditions of one or more of the plurality of interconnected gate elements are generated and incorporated into the circuit design model.