Clock Gating Circuit for Self-Timed Circuits Preventing Glitches
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Solution Overview
Problem
Self-timed circuits face issues with out-of-spec clock operations due to variations in process/voltage/temperature and device aging, leading to potential miscalculations or physical damage, as conventional solutions are not adaptable and often result in glitches.
Innovation Solution
A clock gating circuit with an enabling signal controller, set signal generator, reset signal generator, and feedback section that generates an enabling signal to gate the clock signal based on internal signals, preventing premature clock cycles and producing an acknowledgement signal to higher circuits during blocking periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock gating solutions are used to block out-of-spec clock operations, then clock mismatch can be reduced, but the circuit still experiences glitches during clock signal transitions and lacks adaptability to varying circuit specifications
Solution Approach 1:
The circuit performs preliminary actions by generating set and reset signals in advance based on clock edge detection and completion status. The SR latch is pre-configured with these signals to ensure proper clock gating state before the actual clock transition occurs, preventing glitches during critical transitions.
Solution Approach 2:
The circuit implements feedback by using the completion signal to control the reset signal generation. The feedback section monitors the clock signal and enabling signal to generate feedback that adjusts the reset timing, ensuring the clock gate remains closed until the previous operation is truly complete, thereby eliminating glitches.
2Reliability
If the clock signal is blocked to prevent out-of-spec operations, then circuit safety is improved, but the response time and area efficiency are reduced due to centralized control
Solution Approach 1:
The clock gating function is segmented and distributed to individual sub-circuits rather than being centralized. Each sub-circuit has its own clock gate controlled by local completion signals, allowing independent and immediate response to out-of-spec conditions without waiting for centralized control decisions.
Solution Approach 2:
Each sub-circuit serves itself by generating local completion signals that directly control its own clock gate. The circuit autonomously detects out-of-spec conditions and blocks its own clock signal without external intervention, achieving both safety and fast response time.
3Adaptability or versatility
If traditional clock distribution is used in self-timed circuits, then global synchronization is avoided, but clock mismatch still occurs due to PVT variations and device aging
Solution Approach 1:
The clock gating control is made dynamic by continuously monitoring the completion signal and clock edge relationships. The set and reset signals are dynamically generated based on real-time detection of clock transitions and operation completion status, allowing the circuit to adapt to PVT variations and aging effects while maintaining timing accuracy.
Data Source
AI summary
A clock gating method and circuit for avoiding out-of-spec clock operations. The circuit comprises a clock gating section that gates a clock signal according to an enabling signal generated by an enabling signal controller, the enabling signal controller generating the enabling signal according to a set signal and a reset signal. The circuit further comprises a set signal generator that generates the set signal, a reset signal generator that generates the reset signal, and a feedback section that uses the enabling signal to generate the feedback signal for the reset signal generator. The reset signal generator generates the reset signal by using the feedback signal. The enabling signal controller further generates an acknowledgement signal having a high signal during a blocking period when the clock signal is blocked and utilizes the acknowledgement signal as an announcement to a higher circuit that the clock signal is blocked.