Clock Gating Verification via Output Convergence
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Solution Overview
Problem
Current formal verification methods in electronic design automation face challenges in efficiently reducing power consumption and proving the equivalence of clock gating schemes in digital integrated circuits, as they often require complex and time-consuming equivalence checks between enabled and disabled clock gating configurations.
Innovation Solution
A computer-implemented method that selectively disables clocks associated with specific flip-flops without changing their values, partitions clocks into cascaded clocks, and determines output convergence, using quasi-static variables and dedicated enable/disable logic to simplify the verification process by breaking down the problem into smaller equivalence problems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification uses traditional equivalence checking methods to verify clock gating schemes, then verification completeness is improved, but verification time and complexity increase significantly
Solution Approach 1:
The patent segments the verification process into two independent stages: (1) functional equivalence verification between original and clock-gated designs, and (2) convergence verification of flip-flop outputs. This segmentation allows each stage to use optimized verification methods, reducing overall verification time while maintaining completeness.
Solution Approach 2:
The patent applies preliminary clock gating transformations to the design before formal verification begins. By pre-applying clock gating and using quasi-static variable assignments to model clock behavior, the verification process starts from a transformed state that reduces the complexity of equivalence checking.
2Use of energy by moving object
If clock gating is applied to reduce power consumption, then energy efficiency is improved, but verification complexity increases due to need to prove equivalence between enabled and disabled configurations
Solution Approach 1:
The patent changes the verification approach by introducing convergence verification as a new parameter metric. Instead of traditional equivalence checking that compares entire circuit behaviors, the method verifies convergence of flip-flop output values, simplifying the verification complexity while maintaining power reduction benefits.
Solution Approach 2:
The patent extracts the essential verification requirement from complex equivalence checking to a simpler convergence check of flip-flop outputs. By taking out only the critical verification element (output convergence) rather than verifying entire clock gating configurations, the method reduces verification complexity while preserving power optimization.
3Measurement precision
If equivalence checking is performed between enabled and disabled clock gating configurations, then verification accuracy is improved, but computational resources and time consumption increase
Solution Approach 1:
The patent introduces dynamic convergence verification that adapts to the clock gating configuration. By using quasi-static variable assignments and dynamically modeling clock behavior, the verification process maintains accuracy while improving efficiency through adaptive verification strategies rather than static equivalence checking.
Solution Approach 2:
The patent creates a simplified verification model that copies only the essential flip-flop output behavior rather than replicating entire clock gating configurations. This copying approach maintains verification accuracy by preserving critical signal paths while reducing computational overhead through simplified modeling.
Data Source
AI summary
The present disclosure relates to a method for reducing power consumption. Embodiments include providing an electronic design of a device under test having a plurality of flip-flops associated therewith. Embodiments also include selecting a first set of flip-flops from the plurality of flip-flops and disabling a first clock associated with the first set of flip-flops without changing a value of the first set of flip-flops. Embodiments may further include selecting a second set of flip-flops from the plurality of flip-flops and disabling a second clock associated with the second set of flip-flops without changing a value of the second set of flip-flops. Embodiments may further include determining whether a first output from the first set of flip-flops and a second output from the second set of flip-flops have converged.