Clock-Gating Synchronization Circuit for Cross-Domain Power Control
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Solution Overview
Problem
The integration of clock-gating technology into conventional cross-clock domain synchronization circuits complicates the design and increases gate count, leading to higher manufacturing costs in low-power integrated circuits.
Innovation Solution
A clock-gating synchronization circuit and method that includes a synchronization circuit and a clock-gating circuit, utilizing D flip-flops, XOR gates, multiplexers, and isolated clock-gating cells to perform clock gating and synchronization operations across different clock domains, ensuring proper clock enablement and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock-gating technology is integrated into conventional cross-clock domain synchronization circuits, then power consumption is reduced, but device complexity and gate count increase
Solution Approach 1:
The patent merges the clock-gating functionality with the cross-clock domain synchronization circuit by sharing the same D flip-flops and logic gates for both synchronization and clock-gating operations. The synchronization circuit's output signals are directly used to control the clock-gating enable signal, eliminating the need for separate clock-gating control logic and reducing overall gate count while maintaining power-saving capabilities
Solution Approach 2:
The D flip-flops and logic gates in the synchronization circuit are designed to serve dual purposes: performing cross-clock domain synchronization and generating clock-gating control signals. This multi-functionality allows the same hardware resources to achieve both synchronization and power management goals without increasing device complexity
2Use of energy by moving object
If clock-gating design is added to conventional cross-clock domain synchronization circuit, then power consumption is reduced, but manufacturing cost increases
Solution Approach 1:
The patent combines clock-gating control logic with the existing synchronization circuit elements, using the same D flip-flops and logic gates to generate both synchronized signals and clock-gating enable signals. This integration reduces the total gate count and simplifies the manufacturing process, thereby lowering manufacturing costs while achieving power-saving benefits
3Reliability
If isolated clock-gating cell is used to deal with cross-clock domain, then clock domain isolation is achieved, but synchronization circuit complexity increases
Solution Approach 1:
The patent integrates the clock-gating cell within the synchronization circuit structure, sharing D flip-flops and logic gates between synchronization and clock-gating functions. The clock-gating enable signal is generated directly from the synchronization circuit's output, eliminating the need for separate isolated clock-gating control logic and reducing overall circuit complexity while maintaining proper clock domain isolation
Data Source
AI summary
A clock-gating synchronization circuit is provided. The clock-gating synchronization circuit includes a synchronization circuit and clock-gating circuit. The synchronization circuit is configured to perform a synchronization operation to convert a first control signal in a first clock domain into a second control signal in a second clock domain, transmit the second control signal to an electronic circuit, and determine whether the first control signal and the second control signal are the same to generate a first signal. The clock-gating circuit is configured to perform clock gating on the clock signal from a clock generator in the second clock domain according to the first signal to generate a gated clock signal, and transmit the gated clock signal to the electronic circuit and the synchronization circuit, wherein the synchronization operation performed by the synchronization circuit is controlled by the gated clock signal.