Clock Gating Circuit for Display Power Reduction
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Solution Overview
Problem
Display devices operating at different frame rates face increased power consumption due to clock signal toggling during vertical porch intervals, particularly at lower frame rates like 60 Hz.
Innovation Solution
An integrated circuit with a control signal generator and clock gating circuit that gates the clock signal, stopping toggling during vertical front porch intervals and resuming it after a predetermined horizontal back porch interval, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the vertical porch interval is increased to synchronize frame rates, then frequency transition smoothness is improved, but clock signal toggling increases power consumption
Solution Approach 1:
The patent applies periodic action by gating the clock signal during specific intervals (vertical front porch and horizontal back porch periods) while allowing it to toggle during active display periods. This periodic gating reduces power consumption during non-critical intervals while maintaining frame rate synchronization capability, directly resolving the contradiction between smooth frequency transitions and power consumption
2Reliability
If the clock signal continues toggling during vertical porch interval, then circuit operation is maintained, but power consumption increases
Solution Approach 1:
The patent extracts and removes the clock signal toggling during specific non-critical intervals (vertical front porch and horizontal back porch) while maintaining it during active periods. This selective removal reduces power consumption without affecting circuit operation during critical intervals, resolving the contradiction between reliability and power consumption
Data Source
AI summary
Provided is an integrated circuit capable of gating a clock signal to reduce power consumption during a vertical front porch interval, the integrated circuit including: a control signal generator configured to change a gating control signal from a low level to a high level according to a timing when a data enable signal changes from the high level to the low level, and change the gating control signal from the high level to the low level after a predetermined horizontal back porch interval from a rising edge of a horizontal synchronization signal; and a clock gating circuit configured to stop toggling of a first clock signal input through a first input terminal to output a second clock signal maintained at the low level through a first output terminal when the gating control signal of the high level is input to a control terminal.