Clock Gating Dithering for CMOS Voltage Transient Mitigation
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Solution Overview
Problem
CMOS technology in portable devices is sensitive to voltage changes due to aggressive clock gating, leading to power supply transients when devices are turned on, which can be mitigated by controlling clock signals to manage power variations effectively.
Innovation Solution
A two-stage control method for the clock signal in CMOS circuits, involving selective gating and dithering, where every other clock cycle is initially gated at half speed to allow transients to settle, followed by gradual ramping to full speed to prevent additional voltage fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If aggressive clock gating is employed to preserve battery life, then power consumption is reduced, but voltage transients occur when devices are turned on
Solution Approach 1:
The clock gating strategy is made dynamic by adjusting the gating pattern based on operational state. During startup, no gating is applied to ensure stable voltage. During idle periods, aggressive gating is used to save power. This dynamic adaptation resolves the contradiction between power savings and voltage stability.
Solution Approach 2:
The system performs preliminary action by establishing a ramp-up period during startup where the clock frequency is gradually increased from zero to full speed. This preliminary frequency modulation prevents voltage transients before full operation begins, resolving the contradiction between power efficiency and voltage stability during critical startup phases.
2Duration of action of moving object
If clock signals are turned off during inactivity, then battery life is extended, but large current changes are drawn from the supply
Solution Approach 1:
Instead of abrupt on/off switching, the system employs periodic frequency modulation during the ramp-up phase. The clock frequency is increased in periodic steps (e.g., doubling frequency each period) rather than sudden jumps. This periodic action smooths current changes while still achieving battery life extension through idle gating.
Solution Approach 2:
The system dynamically adjusts clock frequency based on operational state rather than using fixed on/off gating. During ramp-up, frequency increases progressively; during idle periods, frequency is reduced or gating is applied. This dynamic approach extends battery life while minimizing abrupt current changes that would otherwise occur with aggressive gating.
3Reliability
If additional voltage is provided to compensate for voltage loss, then voltage stability is maintained, but the benefits of low operation voltages are negated
Solution Approach 1:
The system performs preliminary frequency modulation during startup to prevent voltage drops before they occur. By gradually ramping up clock frequency and managing power consumption proactively, the system maintains voltage stability through controlled power delivery rather than requiring additional voltage compensation, thus preserving the benefits of low operation voltages.
4Productivity
If clock frequency is increased rapidly to full speed, then operational performance is improved, but voltage transients are introduced
Solution Approach 1:
The system performs preliminary frequency modulation by gradually increasing clock frequency from zero to full speed during a ramp-up period. This preliminary gradual frequency increase prevents voltage transients that would otherwise occur with rapid frequency jumps, resolving the contradiction between operational performance and voltage stability.
Solution Approach 2:
The clock frequency is dynamically adjusted during startup rather than being abruptly set to full speed. The frequency increases progressively through defined periods (e.g., doubling each period), allowing the power supply to adapt. This dynamic frequency management maintains voltage stability while still achieving full operational performance.
Data Source
AI summary
A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period.