Clock Gating Cell With Dual Discharge Paths for Faster Activation
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Solution Overview
Problem
As semiconductor integrated circuits become more complex, the power consumption of flip-flops and clock gating cells remains high, affecting operating speed and efficiency, especially as operating frequency increases.
Innovation Solution
An integrated clock gating cell with multiple discharge paths, including a feedback inverter that performs both feedback and discharge functions, is designed to reduce power consumption and enhance operating speed by improving the time required for the output clock signal to activate after the input clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional clock gating cells are used, then basic clock gating function is provided, but power consumption is high and operating speed is limited
Solution Approach 1:
The clock gating cell is divided into multiple independent discharge paths (first discharge path with first NMOS transistor, second discharge path with second NMOS transistor) that can operate independently. This segmentation allows simultaneous discharge through multiple paths, reducing the overall discharge time and improving operating speed while maintaining low power consumption through selective activation of discharge paths based on enable signal transitions.
Solution Approach 2:
The invention implements dynamic discharge path selection where the first discharge path is activated on enable signal rising edges and the second discharge path is activated on enable signal falling edges. This dynamic adaptation to signal transition directions optimizes the discharge timing, reducing activation time and improving operating speed without unnecessary continuous discharge that would increase power consumption.
2Loss of time
If single discharge path is used, then circuit complexity is reduced, but activation time of output clock signal increases
Solution Approach 1:
The feedback inverter is merged to perform dual functions: providing feedback to the latch circuit for proper timing control and simultaneously acting as a discharge path. This merging reduces the need for separate dedicated discharge transistors, thereby reducing overall circuit complexity while maintaining fast activation time through the combined feedback-discharge mechanism.
Solution Approach 2:
The feedback inverter serves multiple purposes: it provides the necessary feedback signal to the latch circuit for timing control and simultaneously functions as a discharge path for the output node. This multi-functionality reduces the total number of components needed, lowering circuit complexity while achieving fast activation time through the integrated feedback-discharge path.
Data Source
AI summary
A clock gating cell includes an input logic/latch circuit, a keeper logic/signal generating circuit, and an output driver. The input logic/latch circuit generates an internal enable signal based on first and second input enable signals, and generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal. The keeper logic/signal generating circuit is connected between the first node and a second node, includes a feedback path feeding back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes first and second paths discharging the second node. The first and second paths are different. The second path is connected to the feedback path. The output driver generates an output clock signal based on the second internal signal.