Clock Gating Circuit for DUT Testing in Low Power Mode

Solution Overview

Problem

Existing electronic devices face challenges in testing device under test (DUT) circuits while operating in low power mode, as enabling low power circuits for testing introduces additional power consumption.

Innovation Solution

The implementation of a combo clock gated circuit that controls the enablement of primary and secondary clocks using primary and secondary enable signals, allowing the DUT circuit to operate even when the device is in power saving mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the low power circuit is enabled to test the DUT circuit, then the DUT circuit can be tested, but additional power consumption is introduced

Engineering Contradiction:

ImproveDUT circuit testing capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The clock distribution system is segmented into multiple independent clock domains (primary clock domain for function circuits, secondary clock domain for DUT circuit). Each domain can be independently enabled or disabled through separate gating circuits, allowing the DUT circuit to be tested with its own secondary clock while the primary clock domain remains disabled to save power.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically adjusts clock distribution based on operational mode. The gating circuits respond to enable signals that reflect the current operational state (normal operation vs. testing mode), allowing the clock network to adapt its configuration and power consumption accordingly.

Inventive Principle:

Principle #15Dynamics

2Use of energy by moving object

If the primary clock is disabled to save power, then power consumption is reduced, but the DUT circuit cannot be tested

Engineering Contradiction:

Improvepower consumptionVSAvoidDUT circuit testing capability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The clock distribution system is segmented into multiple independent clock domains (primary clock domain for function circuits, secondary clock domain for DUT circuit). Each domain can be independently enabled or disabled through separate gating circuits, allowing the DUT circuit to be tested with its own secondary clock while the primary clock domain remains disabled to save power.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The gating circuit is designed with multi-functionality to handle both primary and secondary clock domains. It can selectively enable/disable clocks based on different operational requirements, serving both power saving mode and testing mode through a single unified control mechanism.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12320846B2Electronic device and method for performing clock gating in electronic device

Publication Date: 2025.06.03 REALTEK SEMICON CORP

AI summary

An electronic device and a method for performing clock gating in the electronic device are provided. The electronic device includes at least one function circuit, a device under test (DUT) circuit and at least one gating circuit. The function circuit is configured to operate according to at least one primary clock, and the DUT circuit is configured to operate according to at least one secondary clock. In addition, the clock gating circuit is configured to control whether to enable the primary clock according to at least one primary enable signal, and control whether to enable the secondary clock according to the primary enable signal and a secondary enable signal.