Hierarchical Clock Gating via E-Graph Rewriting
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Solution Overview
Problem
Existing clock gating techniques in semiconductor design are limited by their reliance on mux tree analysis, which fails to identify non-mux based opportunities for power saving, leading to sub-optimal power management in computing systems.
Innovation Solution
A framework for constructing hierarchical clock gating architectures via e-graph rewriting, which transforms RTL representations into multiplexors to enable more complex clock gating signals and detect non-mux based opportunities, while retaining the original RTL implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If automated clock gating relies on mux tree analysis, then simple register enable signals can be constructed, but non-mux based clock gating opportunities are missed
Solution Approach 1:
The patent introduces an intermediary transformation step that converts RTL representations into multiplexor equivalents. This intermediary representation enables the application of rewriting techniques to detect clock gating opportunities that are not visible in the original RTL form, thereby bridging the gap between simple implementation and enhanced detection capability.
Solution Approach 2:
The patent transforms the representation parameters of the circuit design by converting RTL code into multiplexor-based representations. This parameter change allows rewriting techniques to be applied, enabling detection of non-mux based clock gating opportunities while maintaining the original RTL implementation through the transformation process.
2Device complexity
If clock gating opportunities are limited to mux tree analysis, then the analysis process remains simple, but power saving opportunities are lost
Solution Approach 1:
The patent segments the clock gating detection process into distinct phases: RTL-to-multiplexor transformation, rewriting-based analysis on the transformed representation, and synthesis of clock gating signals. This segmentation allows complex analysis techniques to be applied without overwhelming the overall process, enabling comprehensive power optimization while managing analysis complexity through structured decomposition.
3Adaptability or versatility
If hierarchical clock gating architectures are constructed via rewriting, then non-mux based opportunities are detected, but the construction process becomes more complex
Solution Approach 1:
The patent performs preliminary transformation of RTL representations into multiplexor equivalents before applying rewriting techniques. This preliminary action prepares the design in a form that is amenable to systematic rewriting-based analysis, enabling comprehensive detection of clock gating opportunities across different circuit structures while managing construction complexity through pre-processing.
Data Source
AI summary
Described herein is a technique to enable the construction of hierarchical clock gating architectures via e-graph rewriting. Automated clock gating relies on multiplexor (mux) tree analysis and constructs simple register enable signals. A framework is provided to detect non-mux based opportunities and construct more complex clock gating signals.