Clock Gating Enable Generation for Pipeline Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock-gating methods for mobile device chips fail to efficiently reduce dynamic power consumption by not fully disabling the clock signal during periods of inactivity, such as bubbles within active lines, and face scalability issues due to increased propagation delays and fan-in as pipeline depth increases.
Innovation Solution
A clock-gating system that includes a clock controller which tracks input and output packets to determine whether to gate or pass the clock signal, enabling more precise control by disabling the clock during empty pipeline conditions and maintaining scalability through reduced fan-in, allowing for efficient power conservation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If clock signal is continuously passed to the pipeline, then operational timing is maintained, but dynamic power consumption increases
Solution Approach 1:
The clock gating device dynamically switches between passing and gating the clock signal based on real-time pipeline status. The device monitors pipeline occupancy and adaptively controls clock signal transmission, transitioning from a static continuous clocking approach to a dynamic conditional approach that optimizes power consumption while maintaining operational reliability.
Solution Approach 2:
The system implements feedback control by monitoring pipeline status (occupied vs. empty states) and using this information to control the clock gating device. The device receives status signals from the pipeline and adjusts its behavior accordingly, creating a closed-loop control system that ensures the clock signal is gated only when safe to do so, thereby maintaining operational timing while reducing power consumption.
2Measurement precision
If clock gating control checks each pipeline stage, then power reduction precision is improved, but device complexity increases
Solution Approach 1:
The patent merges the clock gating control functionality into a single centralized device that receives consolidated status information from the pipeline. Instead of implementing separate control logic at each pipeline stage, the system combines all status monitoring and clock gating decisions into one unit, reducing overall device complexity while maintaining the ability to precisely control power reduction based on pipeline occupancy.
Solution Approach 2:
The clock gating device acts as an intermediary between the pipeline stages and the clock signal source. It receives status information from the pipeline (without requiring complex control logic at each stage) and mediates the clock signal transmission accordingly. This intermediary approach simplifies the control architecture while enabling precise power reduction based on actual pipeline occupancy.
3Productivity
If pipeline depth is increased, then processing capability is improved, but propagation delay and fan-in increase
Solution Approach 1:
The patent segments the clock signal distribution into multiple independent clock gating devices, each controlling a specific pipeline stage or group of stages. This segmentation allows each gating device to operate with reduced fan-in and lower propagation delay, while the overall pipeline maintains high processing capability through the coordinated operation of multiple segmented clock gating units.
Data Source
AI summary
In one embodiment, a clock-gating system for a pipeline includes a clock-gating device configured to gate or pass a clock signal to the pipeline, and a clock controller. The clock controller is configured to track a number of input packets at an input of the pipeline, to track a number of output packets at an output of the pipeline, to determine whether to gate or pass the clock signal based on the number of the input packets and the number of the output packets, to instruct the clock-gating device to pass the clock signal if a determination is made to pass the clock signal, and to instruct the clock-gating device to gate the clock signal if a determination is made to gate the clock signal.