Automated Clock-Gating Insertion in Microprocessor Feedback Paths

Solution Overview

Problem

Automated tools fail to effectively identify and implement clock-gating opportunities in microprocessor circuits, leading to inefficiencies in power consumption and heat management due to manual limitations and oversight of potential clock-gating scenarios during optimization processes.

Innovation Solution

A method and system that automatically identify feedback paths in clocked memory elements, gate clock signals through combinational logic, and cluster clock-gated elements to share common signals, enabling efficient clock-gating logic insertion and propagation without manual intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If automated tools are used to identify clock-gating opportunities, then productivity is improved, but manufacturing precision deteriorates due to failure to identify all clock-gating opportunities

Engineering Contradiction:

Improveautomation of clock-gating identificationVSAvoidcompleteness of clock-gating opportunity identification

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent performs logic optimization and mapping operations before clock-gate insertion to prepare the circuit in a state where all clock-gating opportunities are visible and identifiable to automated tools, preventing oversight of potential clock-gating scenarios

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism where clock-gating insertion is performed, then the circuit is re-analyzed to identify additional clock-gating opportunities that were previously obscured, and the process is repeated until no further opportunities remain, ensuring complete identification

Inventive Principle:

Principle #23Feedback

2Device complexity

If logic optimization is performed before clock-gate insertion, then device complexity is reduced, but measurement precision deteriorates due to obscured clock-gating opportunities

Engineering Contradiction:

Improvecircuit optimizationVSAvoiddetection of clock-gating opportunities

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent performs logic optimization and mapping operations before clock-gate insertion to prepare the circuit in a state where all clock-gating opportunities are visible and identifiable to automated tools, preventing oversight of potential clock-gating scenarios

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism where clock-gating insertion is performed, then the circuit is re-analyzed to identify additional clock-gating opportunities that were previously obscured, and the process is repeated until no further opportunities remain, ensuring complete identification

Inventive Principle:

Principle #23Feedback

3Manufacturing precision

If manual clock-gating identification is used, then manufacturing precision is improved, but productivity deteriorates due to time-consuming process

Engineering Contradiction:

Improveaccuracy of clock-gating identificationVSAvoidspeed of clock-gating implementation

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent employs automated tools that perform clock-gating identification and insertion without manual intervention, making the system self-sufficient in identifying clock-gating opportunities while maintaining high accuracy through multi-pass analysis and feedback mechanisms

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS8132144B2Automatic clock-gating insertion and propagation technique

Publication Date: 2012.03.06 ORACLE AMERICAN INC

AI summary

Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a circuit which includes a plurality of clocked memory elements. Next, the system identifies a feedback path from an output of a clocked memory element to an input of the clocked memory element, wherein the feedback path passes through intervening combinational logic, but does not pass through other clocked memory elements in the circuit. Then, the system gates a clock signal to the clocked memory element so that the clock signal is disabled when the feedback path causes a value which appears at the output of the clocked memory element to be appear at the input of the clocked memory element.