Synchronized Clock Gating for FIFO Pointer Alignment
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Solution Overview
Problem
Existing integrated circuits face challenges in maintaining timing relationships between write and read pointers during clock gating in low power modes, leading to the need for retraining when exiting these modes.
Innovation Solution
The implementation of a synchronized clock gating mechanism that aligns a slow clock signal with a fast clock signal, using a delay-locked loop to ensure that the fast clock is gated for integer multiples of the slow clock cycle, thereby maintaining timing relationships between FIFO buffer write and read pointers without requiring retraining.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clock gating is implemented to reduce power consumption in low power modes, then power consumption is reduced, but timing relationships between write and read pointers are lost requiring retraining
Solution Approach 1:
A synchronization circuit is introduced as an intermediary between the asynchronous clock gating signal and the clocked storage elements. This synchronization circuit includes a register that captures the gating control signal on the rising edge of the fast clock, ensuring that the gating action is coordinated with the clock phases and maintains timing relationships between write and read pointers during low power modes
Solution Approach 2:
The synchronization circuit prepares and aligns the clock gating signal before it is applied to the serialization circuitry. By synchronizing the gating control signal to the fast clock phase, the system ensures that timing relationships are established in advance, eliminating the need for retraining when exiting low power modes
2Loss of energy
If the fast clock is gated without synchronization to the slow clock, then power savings are achieved, but data path latency becomes inconsistent requiring retraining
Solution Approach 1:
The delay-locked loop establishes a feedback mechanism where the slow clock signal is used to generate a delayed version that is synchronized with the fast clock. This feedback loop ensures that the gating duration is precisely controlled as an integer multiple of the slow clock cycle, maintaining consistent data path latency
Solution Approach 2:
The system changes the parameter of clock gating from an asynchronous operation to a synchronized one where the gating duration is precisely defined as an integer multiple of the slow clock cycle. This parameter change ensures that data path latency remains consistent even when the fast clock is gated, eliminating the need for retraining
Data Source
AI summary
During a low power mode, a fast clock may not be provided to serial/parallel conversion circuitry. An asynchronous gating signal that controls the gating of the fast clock may be synchronized to a slow clock and the fast clock. The frequency of the fast clock may be an integer multiple of the slow clock, such that gating the fast clock based on the fast-slow clock synchronized gating signal results in the gating of the fast clock lasting for a duration that may be an integer multiple of the serialization factor multiplied by the conversion circuitry FIFO buffer depth. This maintains the relationship between the FIFO buffer's read and write pointers and associated clocking circuitry during the clock shutoff period. By maintaining these relationships during the clock shutoff period, the serial/parallel conversion circuitry may enter and exit the low power mode without requiring retraining as data path latencies remain unchanged.