Clock Gating Frequency Control Without Operation Suspension
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Solution Overview
Problem
Existing integrated circuits face challenges in dynamically changing clock frequencies without suspending operations, which can lead to inefficiencies in power consumption and performance, especially when workload demands vary.
Innovation Solution
The implementation of a clock-gating unit that dynamically adjusts the clock frequency by altering the enable signal's duty cycle, allowing the clock signal to be reduced in frequency without suspending operations, using a combination of coarse and fine-grain clock-gating units and a clock control unit to manage the clock signal distribution across multiple functional units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If frequency scaling is used to change clock frequency, then power consumption is reduced when workload is low, but operations must be suspended during frequency transition
Solution Approach 1:
The patent segments the clock-gating function into two hierarchical levels: coarse clock-gating units that control groups of functional blocks and fine-grain clock-gating units that control individual functional blocks. This segmentation allows selective frequency reduction in specific regions without suspending operations across the entire processor, resolving the contradiction between power savings and operational continuity.
Solution Approach 2:
The patent implements periodic clock signal distribution where the clock signal is distributed periodically to functional blocks through the coarse and fine-grain clock-gating units. This periodic action enables dynamic frequency adjustment without requiring complete operation suspension, as the clock gating occurs in a rhythmic, controlled manner that maintains operational continuity.
2Loss of energy
If traditional clock-gating logic is added at leaf nodes, then power saving is achieved when circuitry is idle, but device complexity increases due to extra hardware
Solution Approach 1:
The patent merges the clock-gating control function into existing clock distribution infrastructure by introducing coarse clock-gating units at strategic points in the clock tree rather than adding separate control logic at every leaf node. This merging approach achieves power saving functionality while minimizing additional hardware complexity by consolidating control functions.
Solution Approach 2:
The coarse clock-gating units serve multiple functions: they control clock distribution to multiple functional blocks simultaneously, enable dynamic frequency scaling, and provide hierarchical power management. This multi-functionality reduces the need for dedicated control logic at each leaf node, thereby reducing overall device complexity while maintaining power saving capabilities.
3Loss of energy
If clock frequency is reduced to save power, then power consumption decreases, but processing speed is reduced
Solution Approach 1:
The patent implements dynamic clock frequency adjustment where the clock frequency is continuously adapted based on actual workload conditions. The coarse and fine-grain clock-gating units dynamically modify clock distribution in response to operational demands, allowing the system to operate at reduced frequencies during low-workload periods (saving power) and full frequencies during high-workload periods (maintaining speed), thus resolving the contradiction between power consumption and processing speed.
Solution Approach 2:
The patent changes the clock frequency parameter dynamically based on workload conditions. By adjusting the frequency parameter of the clock signal distributed to functional blocks, the system can optimize the balance between power consumption and processing speed, reducing frequency when power savings are prioritized and maintaining full frequency when performance is critical.
Data Source
AI summary
A method and apparatus for controlling the frequency of a clock signal using a clock-gating circuit is disclosed. In one embodiment, a root clock signal and an enable signal are provided to a clock-gating circuit. The clock-gating circuit is configured to provide an operational clock signal (based on the root clock signal) when the enable signal is asserted. The operational clock signal is inhibited when the enable signal is de-asserted. The frequency of the operational clock signal can be output at a reduced frequency (relative to the root clock signal) by asserting the enable signal for one of every N clock cycles. Furthermore, the frequency of the operational clock signal can be dynamically changed by changing the rate of asserting the enable signal relative to the root clock signal, without suspending operation of a functional unit receiving the operational clock signal.