Integrated Clock Gating With Frequency Division for Lower Clock Power
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Solution Overview
Problem
Modern microprocessors and SoCs face significant power dissipation challenges due to clocking, with dynamic clocking power contributing up to 60% of overall chip power dissipation, limiting further reductions in transistor size and scaling, and necessitating innovative solutions to improve performance and reduce power consumption.
Innovation Solution
The implementation of an integrated clock gate circuit that facilitates mixed frequency clocking by enabling dual-edge triggered flip-flops within single-edge triggered flip-flop designs, using combinatorial logic and feedback paths to selectively gate clock signals and reduce power consumption through frequency division.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock frequency is increased to improve performance, then processing speed improves, but power dissipation increases
Solution Approach 1:
The patent applies periodic action by using dual-edge triggered flip-flops that operate at twice the frequency of the input clock signal. The clock gate circuit selectively enables edges of the clock signal, allowing sequential logic to be triggered on both rising and falling edges. This periodic triggering mechanism enables higher effective processing speed without proportionally increasing continuous power dissipation, as the circuit leverages both edges of the clock cycle efficiently.
Solution Approach 2:
The patent changes the operational parameter of the flip-flop circuit by transitioning from single-edge triggering to dual-edge triggering. This parameter change allows the same clock signal to drive twice as many operations per cycle, effectively doubling the processing speed without increasing clock frequency or power consumption. The clock gate circuit dynamically adjusts which edges trigger the flip-flops based on control signals.
2Area of stationary object
If transistor size is reduced to improve area efficiency, then silicon cost and PCB footprint decrease, but power/leakage control becomes more difficult
Solution Approach 1:
The patent segments the clocking function by introducing a clock gate circuit that selectively controls clock signal distribution to different flip-flops. This segmentation allows independent control of clocking to various circuit blocks, enabling precise power management. By gating the clock signal to only those flip-flops that need to operate, the patent reduces unnecessary switching activity and leakage power in inactive regions, even when transistors are scaled down.
Solution Approach 2:
The patent introduces dynamic control through the clock gate circuit, which can adaptively enable or disable clock signaling to different flip-flop groups based on operational requirements. This dynamic gating mechanism allows the system to optimize power consumption in real-time by activating only the necessary circuit blocks, thereby managing leakage power effectively in scaled transistor designs.
3Use of energy by moving object
If dual-edge triggered flip-flops are used to improve frequency efficiency, then clocking power reduces, but circuit complexity increases
Solution Approach 1:
The patent introduces a clock gate circuit as an intermediary between the clock source and the dual-edge triggered flip-flops. This intermediary component selectively controls which edges of the clock signal trigger the flip-flops, enabling power-efficient operation without requiring complex modifications to the flip-flop internal structure. The clock gate absorbs the complexity, allowing the use of standardized dual-edge triggered flip-flop cells while maintaining control over power consumption.
Solution Approach 2:
The patent employs universal dual-edge triggered flip-flop cells that can operate in multiple modes (single-edge or dual-edge triggering) based on control signals from the clock gate circuit. This multi-functionality allows the same flip-flop design to be used throughout the circuit, reducing overall complexity by avoiding the need for different flip-flop types. The clock gate circuit provides the flexibility to optimize power consumption without requiring specialized circuit designs.
Data Source
AI summary
Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality. In an embodiment, an ICG circuit comprises first circuitry which is coupled to receive a first clock signal, and second circuitry which is coupled to receive a control signal. The first circuitry provides a single edge triggered flip-flop functionality, and is coupled to communicate a feedback signal which the first circuitry is further coupled to receive. Based on the control signal and the feedback signal, the second circuitry performs an exclusive OR (XOR) operation to selectively enable the first circuitry to generate a second clock signal based on the first clock signal. In another embodiment, a frequency of the second clock signal is substantially equal to one half of a frequency of the first clock signal.