Clock Gating for Dynamic Frequency Scaling Without Suspension
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Solution Overview
Problem
Existing clock-gating techniques in integrated circuits require suspension of operations to change clock frequencies, leading to inefficiencies in power management and performance.
Innovation Solution
A method and apparatus that dynamically change clock frequencies using a clock-gating unit, where coarse and fine-grain clock-gating units receive enable signals to adjust the operational clock signal's frequency and duty cycle without suspending operations, allowing for power savings by reducing frequency when workload is low.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If frequency scaling is implemented by suspending processing operations and changing clock frequency at source, then clock frequency can be adjusted, but system productivity is reduced due to operational suspension
Solution Approach 1:
The patent segments the clock distribution system into multiple independent clock domains, each controlled by its own clock-gating unit. This allows different functional blocks to operate at different clock frequencies simultaneously, enabling frequency scaling without suspending entire system operations. The segmentation of clock control enables selective frequency adjustment in specific blocks while others continue running at full speed.
Solution Approach 2:
The patent implements dynamic clock frequency adjustment by allowing clock-gating units to change operational clock frequency on-the-fly based on workload conditions. The system can dynamically transition between full frequency and reduced frequency (e.g., 1/N frequency) without suspension, adapting clock speed to actual processing needs in real-time while maintaining system productivity.
2Use of energy by moving object
If traditional clock-gating logic is added at leaf nodes to save power, then power consumption is reduced, but device complexity increases due to additional hardware
Solution Approach 1:
The patent makes clock-gating units multi-functional by enabling them to perform both traditional clock gating (enable/deassert functionality) and frequency scaling (operational frequency adjustment) operations. This universal clock-gating unit can operate in full-frequency mode or reduced-frequency mode (1/N frequency) based on workload, eliminating the need for separate frequency scaling hardware and reducing overall device complexity.
Solution Approach 2:
The patent merges frequency scaling functionality with existing clock-gating logic into a unified clock-gating unit. By combining these functions, the system avoids adding separate frequency scaling hardware at each leaf node, thereby reducing device complexity while achieving both power savings and frequency adjustment capabilities.
3Loss of energy
If clock frequency is reduced to save power during low workload, then power consumption is reduced, but loss of time occurs due to operational suspension in traditional methods
Solution Approach 1:
The patent ensures continuous useful action by allowing the system to transition to reduced clock frequency (1/N frequency) without suspending operations. The clock-gating unit continuously provides clock signals at the appropriate frequency based on workload, eliminating idle suspension periods and ensuring that processing continues uninterrupted even at reduced speed, thus avoiding time loss while achieving power savings.
Data Source
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AI summary
A method and apparatus for controlling the frequency of a clock signal using a clock-gating circuit is disclosed. In one embodiment, a root clock signal and an enable signal are provided to a clock-gating circuit. The clock-gating circuit is configured to provide an operational clock signal (based on the root clock signal) when the enable signal is asserted. The operational clock signal is inhibited when the enable signal is de-asserted. The frequency of the operational clock signal can be output at a reduced frequency (relative to the root clock signal) by asserting the enable signal for one of every N clock cycles. Furthermore, the frequency of the operational clock signal can be dynamically changed by changing the rate of asserting the enable signal relative to the root clock signal, without suspending operation of a functional unit receiving the operational clock signal.