Clock Gating Circuit for Harmonic Interference Mitigation in Mixed-Signal ICs
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Solution Overview
Problem
In mixed signal Integrated Circuits (ICs), digital switching transients cause interference with analog circuits, leading to performance degradation in victim blocks due to harmonic coupling, making it challenging to find a frequency that is compatible for all radio circuitries.
Innovation Solution
A clock generation circuit is implemented that gates a higher frequency clock signal to generate a third clock signal with an average frequency matching the original clock signal, using a gating circuit, FIFO buffer, and control circuit to minimize harmonic interference with victim blocks by randomly gating clock cycles based on occupancy levels and random numbers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a first clock signal is used to operate the aggressor block, then the aggressor block functions properly, but harmonics of the first clock signal interfere with the frequency range of victim blocks
Solution Approach 1:
The harmful harmonic components are extracted and removed from the clock signal spectrum by replacing the first clock signal with a third clock signal generated through gating a second clock signal, such that the resulting signal has an average frequency matching the original but with harmonics shifted away from victim block frequency ranges
Solution Approach 2:
The clock signal parameters are changed by generating a third clock signal with different spectral characteristics through random gating, while maintaining the average frequency to ensure proper operation of the aggressor block. This changes the frequency domain distribution without affecting the time-averaged operating frequency
2Object-affected harmful factors
If a gating circuit is used to generate a third clock signal to avoid harmonic interference, then interference with victim blocks is reduced, but the device complexity increases
Solution Approach 1:
A gating circuit is introduced as an intermediary component between the second clock signal source and the aggressor block. This gating circuit randomly gates the second clock signal to produce the third clock signal, serving as a mediator that transforms the clock signal characteristics without directly modifying the aggressor block or victim blocks
Solution Approach 2:
The gating circuit applies periodic gating action to the second clock signal, where the gating occurs at intervals determined by random selection. This periodic gating mechanism transforms the continuous second clock signal into a pulsed third clock signal with the desired spectral properties
3Object-affected harmful factors
If random gating based on occupancy levels and random numbers is used, then harmonic interference is minimized, but the control circuit complexity increases
Solution Approach 1:
The control circuit implements feedback by monitoring the occupancy level of the FIFO buffer and using this information to dynamically adjust the gating of the clock signal. The occupancy level feedback ensures that the random gating maintains proper data synchronization while minimizing harmonic interference through adaptive control
Solution Approach 2:
The gating pattern is made dynamic through random selection based on occupancy levels rather than using a fixed periodic pattern. This dynamic approach allows the system to adapt to varying data flow conditions while maintaining the spectral properties that minimize interference with victim blocks
Data Source
AI summary
A clock generation circuit in an IC is provided for mitigating signal interferences caused by an aggressor block operable on a first clock signal with a frequency range of a victim block. The clock generation circuit includes a gating circuit configured to perform gating of a second clock signal to generate a third clock signal based on control signal. An average frequency of the third clock signal is substantially matched to a frequency of the first clock signal, and harmonics of the third clock signal do not interfere with the frequency range of the victim block. The clock generation circuit further includes a FIFO buffer circuit configured to receive the first clock signal as a write clock and the third clock signal as read clock, and a control circuit for generating the control signal based on an occupancy level of FIFO buffer circuit and a plurality of random numbers.