Clock Gating Circuit for IC Transition Fault Testing
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Solution Overview
Problem
Transition fault testing of integrated circuits often results in high peak power due to non-functional test signals, leading to excessive switching activity, voltage drops, and potential damage, which existing solutions like clock gating and functional scan testing struggle to fully mitigate, especially during launch on scan (LoS) transition tests.
Innovation Solution
A circuit and method utilizing a programmable register and multiplexer to selectively provide a clock signal to flip-flops based on scan shift and functional enable signals, reducing peak power by disabling the test enable port from the first capture cycle and using the scan shift signal as a select signal for the multiplexer, thereby controlling clock gating during both launch on capture (LoC) and launch on scan (LoS) transition tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test signals are used in scan tests to identify and locate signal transition faults, then testing capability is improved, but switching activity increases leading to high peak power consumption
Solution Approach 1:
The patent segments the clock signal distribution by introducing a multiplexer that selectively connects the clock signal to different destinations based on the scan shift signal state. During scan shift, the clock is routed to the programmable register; during capture, it is routed to the flip-flops. This segmentation of clock distribution resolves the contradiction by enabling fault testing while controlling peak power through selective clock gating.
Solution Approach 2:
The patent implements dynamic clock gating control where the clock signal path changes based on the operational phase (scan shift vs. capture). The multiplexer dynamically routes the clock signal based on the scan shift signal, and the programmable register is dynamically programmed to de-assert at the end of scan shift. This dynamic adaptation allows the system to maintain testing capability while reducing peak power during capture operations.
2Reliability
If clock signal is provided to all flip-flops during scan capture operation, then test response capture is improved, but peak power consumption increases due to high switching activity
Solution Approach 1:
The patent extracts the test enable (TE) signal function from the conventional clock gating cell and implements it through a programmable register that is de-asserted at the end of scan shift. This extraction allows the system to maintain test response capture capability while removing the source of high peak power during capture operations, as the programmable register prevents unnecessary clock switching to flip-flops during capture.
Solution Approach 2:
The patent introduces a multiplexer as an intermediary between the clock signal source and the flip-flops. This multiplexer, controlled by the scan shift signal, mediates clock distribution by routing the clock to the programmable register during scan shift and blocking it during capture. This intermediary component enables test response capture while controlling peak power through intelligent clock gating.
3Reliability
If high peak currents are used during scan tests, then switching activity is maintained for fault detection, but voltage drops and hot-spots occur causing potential damage
Solution Approach 1:
The patent implements periodic control of the clock signal through the programmable register that is programmed to de-assert at the end of scan shift. This creates a periodic pattern where the clock is enabled during scan shift for fault detection and disabled during capture to prevent voltage drops and hot-spots. This periodic action maintains fault detection capability while eliminating harmful peak currents during capture operations.
Data Source
AI summary
A circuit for reducing peak power during transition fault testing of an integrated circuit (IC) includes a programmable register that receives scan shift and SDI (scan data in) signals. Input and output ports of the programmable register are connected together. A multiplexer is provided that has a first input port that is maintained asserted, and a second input port connected to the output port of the programmable register. A scan shift signal, which remains asserted during a scan shift operation and de-asserted during a scan capture operation, is provided at a select input port of the multiplexer. The output of the multiplexer is provided as an input to a clock gating cell. The clock gating cell selectively provides the clock signal to the scan-chain flip-flops in the IC based on the scan shift signal and a functional enable signal, and reduces peak power during transition fault testing.