Latch-Based Clock Gating to Eliminate Idle Dynamic Power
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Solution Overview
Problem
Digital electronic systems face challenges in reducing power consumption, particularly in clock gating circuits, where dynamic power is consumed due to transistor switching even when the clock gating circuit is not enabled, leading to increased overall power usage.
Innovation Solution
A clock gating circuit is designed with a latch that captures and stores the enabled state of an enable signal, allowing the output signal to hold a predetermined state irrespective of the input clock signal's state, thereby eliminating dynamic power consumption when the latch is not storing the enabled state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the clock gating circuit is disabled to reduce power consumption, then power consumption is reduced, but the clock signal cannot propagate to consumers
Solution Approach 1:
The clock gating circuit dynamically switches between enabled and disabled states based on the enable signal, allowing flexible control of clock propagation. The latch dynamically captures and stores the enabled state, enabling the circuit to adapt its behavior to system requirements while maintaining low power consumption when disabled.
2Reliability
If the clock gating circuit is enabled to allow clock signal propagation, then clock signal reaches consumers, but dynamic power is consumed due to transistor switching
Solution Approach 1:
The harmful dynamic power consumption is extracted and eliminated by designing the circuit such that transistors do not switch when the enable signal is deasserted. The latch isolates the clock signal path from the enable signal path, preventing unnecessary transistor switching and associated power consumption while maintaining clock propagation when needed.
3Ease of operation
If traditional clock gating circuits are used, then clock signal can be gated, but dynamic power is still consumed when the circuit is not enabled
Solution Approach 1:
The latch performs preliminary action by capturing and storing the enabled state of the enable signal before the clock signal arrives. This preliminary capture ensures that the circuit is properly configured to handle the clock signal without unnecessary transistor switching, thereby preventing dynamic power consumption before it occurs.
Data Source
AI summary
A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal.