Clock Gating Control for Image Processing Unit Power Management
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Solution Overview
Problem
Conventional image forming apparatuses experience high power consumption during standby periods due to unnecessary energization of the ASIC, leading to increased power usage and decreased performance in image processing tasks like FCOT (First Copy Time).
Innovation Solution
Implementing a power saving control mechanism using clock gating, where the image processing unit executes initialization processing upon power supply and stops clock supply upon completion, resuming clock supply only when instructed to start a function by the user, thereby reducing standby time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock gating is enabled to save power during standby periods, then power consumption is reduced, but the startup time increases due to necessary register setting
Solution Approach 1:
The patent applies preliminary action by performing register setting in advance during the power supply initialization phase, before the apparatus enters standby mode. This ensures that when the apparatus is activated from standby, the image processing unit is already configured and ready to operate immediately, eliminating startup delay while maintaining power savings through clock gating during standby periods
2Loss of time
If the ASIC is energized continuously to reduce standby time, then startup performance is improved, but power consumption increases during non-use periods
Solution Approach 1:
The patent applies dynamics by implementing dynamic power management that adjusts the energization state of the ASIC based on operational needs. The system transitions between active and standby states dynamically, using clock gating to control power supply to the image processing unit. This allows the apparatus to achieve low power consumption during standby while maintaining quick startup performance when activation is required
3Productivity
If clock gating is disabled immediately after ASIC startup to ensure operability, then image processing performance is improved, but power consumption increases during non-use periods
Solution Approach 1:
The patent applies feedback by implementing a control mechanism that monitors the operational state and usage patterns of the image processing unit. Based on this feedback, the system intelligently determines when to enable or disable clock gating, balancing power consumption and performance requirements. The control unit adjusts clock gating settings dynamically according to actual usage conditions
Data Source
AI summary
This image forming apparatus includes, for example, a first control unit provided on a first control board and configured to comprehensively control the image forming apparatus, a second control unit provided on a second control board different from the first control board and configured to control a function provided by the image forming apparatus, and an image processing unit provided on the second control board and configured to execute image processing. The second control unit causes the image processing unit to execute initialization processing when power is supplied, stops supplying clocks to the image processing unit upon completion of the initialization processing, and resumes supplying clocks to the image processing unit in accordance with generation of a start event of instructing to start a function provided by the image forming apparatus.