Semiconductor Clock Gating for Precise PDN Impedance Measurement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for measuring impedance in power delivery networks using current sinks occupy large on-chip area and induce leakage current, leading to inaccurate impedance measurements due to jitter in gated clock signals.
Innovation Solution
A system comprising a signal generating device that aligns edges of clock and enable signals to generate a gated clock signal, reducing jitter and improving impedance measurement accuracy by using a phase locked loop circuit, divider, digital controlled delay line, phase detector, and isolation clock gating circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a current sink is used to measure impedance in the power delivery network, then the impedance measurement can be performed, but the measurement precision deteriorates due to jitter in the gated clock signal and leakage current
Solution Approach 1:
The patent applies preliminary action by pre-aligning the edges of the clock signal and enable signal using a phase locked loop circuit and digital controlled delay line before generating the gated clock signal. This preliminary synchronization eliminates jitter in the gated clock signal, ensuring accurate impedance measurement without the reliability issues caused by signal misalignment.
2Productivity
If a current sink is used for impedance measurement, then the measurement function is achieved, but the on-chip area occupied increases
Solution Approach 1:
The patent uses a digital controlled delay line that replicates and adjusts the clock signal phases without requiring a physical current sink. This copying approach allows impedance measurement functionality to be achieved through signal processing rather than through current injection, significantly reducing the on-chip area required for the measurement circuit.
3Measurement precision
If a current sink is used to perform impedance measurement, then the measurement can be conducted, but leakage current is induced affecting measurement accuracy
Solution Approach 1:
The patent replaces the mechanical/electrical current sink approach with a signal processing-based impedance measurement method. By using a phase locked loop circuit and digital controlled delay line to generate precisely timed gated clock signals, the system measures impedance through timing analysis rather than current injection, eliminating the leakage current problem entirely.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system enhances impedance measurement precision by minimizing jitter in the gated clock signal, thereby improving the accuracy of impedance plots in power delivery networks.
Implementation Method 1
A system comprising a signal generating device that aligns edges of clock and enable signals to generate a gated clock signal, reducing jitter and improving impedance measurement accuracy by using a phase locked loop circuit
Data Source
AI summary
A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.