Clock Gating Latch Topology With Fewer Clocked Switches
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Solution Overview
Problem
Conventional clock gating latches in integrated circuits (ICs) consume power even when disabling clock signals due to the number of switches that remain clocked, leading to inefficiencies in power consumption.
Innovation Solution
A clock gating latch design that reduces the number of switches remaining clocked by using a propagation circuit, a keeper circuit, and an AND gate with specific switch configurations, allowing the latch to operate with as few as three switches in the enabled mode and fewer overall, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional clock gating latches use multiple switches in propagation and keeper circuits, then the latch can maintain proper clock signal propagation and data holding functionality, but the number of switches remaining clocked increases leading to higher power consumption
Solution Approach 1:
The patent extracts and removes unnecessary switches from the conventional clock gating latch structure. Specifically, it eliminates redundant switches in the propagation circuit (reducing from multiple switches to a single switch) and in the keeper circuit (reducing from multiple switches to a single switch), thereby reducing the number of clocked switches from five or more to just three, which directly reduces power consumption while maintaining essential latch functionality
Solution Approach 2:
The patent merges the functionality of multiple switches into fewer switches by redesigning the propagation circuit and keeper circuit to share common clocked switches. The propagation circuit and keeper circuit are configured to utilize the same set of three switches, eliminating the need for separate dedicated switches in each circuit, thus reducing overall switch count and power consumption
2Loss of energy
If the latch disables clock signal propagation to downstream elements, then clock power consumption is reduced, but the latch itself continues to consume power due to remaining clocked switches
Solution Approach 1:
The patent extracts the essential clock gating functionality from a complex multi-switch structure and implements it using only three switches. By removing redundant switching elements and keeping only the minimum necessary switches in the propagation and keeper circuits, the design achieves effective clock gating with minimal power consumption
Solution Approach 2:
The patent applies local quality by making different parts of the latch have different clocking characteristics. The propagation circuit and keeper circuit are designed such that their switches are selectively clocked based on local requirements - only the essential three switches remain clocked, while other elements are properly decoupled from the clock signal when gating is active
Data Source
AI summary
A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit.