Clock Gating Cell Layout for Lower Latch Input Toggling
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Solution Overview
Problem
Conventional clock gating cells experience high power consumption due to continuous toggling of the clock input signal at the clock input terminal of the latch, leading to excessive charging and discharging of capacitive load, which increases dynamic power dissipation.
Innovation Solution
A clock gating cell design that incorporates a latch circuit and logic circuits, where the clock input signal is gated using a reset signal, preventing continuous toggling when the latch is in a reset state, thereby reducing power consumption by selectively providing the clock signal only when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock input signal continuously toggles at the clock input terminal of the latch, then the storage elements can respond to clock edges, but the capacitive load is repeatedly charged and discharged, causing high dynamic power consumption
Solution Approach 1:
The patent introduces a clock gating cell as an intermediary component between the clock signal source and the latch circuit. This gating cell selectively passes the clock signal to the latch based on enable signals, preventing unnecessary clock toggling at the latch input terminal while maintaining proper storage element response when needed.
Solution Approach 2:
The patent applies different clock signal characteristics to different parts of the circuit. The clock signal is fully active for storage elements that need updating, while it is blocked or gated for storage elements that do not require state changes, optimizing power consumption locally for each functional block.
2Productivity
If the clock gating circuit uses a conventional design with latch and AND gate, then the gated clock signal toggles only when output state changes, but the clock input signal continues to toggle at the latch input terminal, causing continuous capacitive charging and discharging
Solution Approach 1:
The patent extracts the clock signal gating function from the conventional latch-based approach and implements it at an earlier stage in the clock distribution network. By placing gating logic before the latch input terminal, the patent removes unnecessary clock toggling from the latch input while preserving the gated clock functionality for storage elements.
Solution Approach 2:
The patent performs clock signal gating in advance, before the clock signal reaches the latch input terminal. The gating logic evaluates enable signals and selectively passes or blocks the clock signal beforehand, preventing unnecessary toggling at the latch input while ensuring proper timing for storage element updates.
Data Source
AI summary
A system for generating a gated clock signal includes an AND gate and a clock gating cell. The AND gate receives a reset signal and an input clock signal and generates a clock signal that is provided to a clock input terminal of the clock gating cell. The clock gating cell generates a gated clock signal based on an input signal and the clock signal. Gating the clock input to a latch allows a means for conserving power.