Integrated Clock Gating Cell for Low Switching Power
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Solution Overview
Problem
Conventional integrated clock gating cells consume significant clock switching power due to frequent switching activity, which is a challenge in mobile devices where power efficiency is crucial.
Innovation Solution
A low-power low-setup integrated clock gating cell design that replaces latch control signals with internal control signals, using a NOR gate, NAND gate, and inverter configuration to reduce clock switching power and improve enable setup time by enabling complex enable selection logic, thereby making the latch 'transparent' when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional integrated clock gating cells use a clock signal to control a latch, then the latch can be controlled to gate the clock, but the clock switching power consumption increases significantly
Solution Approach 1:
The patent extracts the latch control signals from the clock path by using internal control signals instead. The enable signal is processed through logic gates (NOR, NAND, inverters) to generate control signals that operate independently of the clock signal, removing the clock from the direct control path of the latch and thereby eliminating clock switching power consumption associated with latch control.
Solution Approach 2:
The patent changes the control mechanism from direct clock signal control to internal control signal generation. By using logic gates to generate enable signals (EN, ECK, ECKN) from the original enable input, the system transforms the control parameter from clock-edge triggered to level-based control, reducing unnecessary clock switching while maintaining latch functionality.
2Loss of time
If the latch is made transparent by enabling complex enable selection logic, then the setup time of the enable signal is improved, but the device complexity increases
Solution Approach 1:
The patent implements preliminary action by generating the enable signal early in the clock cycle using logic gates (NOR gate receiving enable and test enable signals, NAND gate, and inverters). The EN signal is prepared before the clock edge arrives, allowing the latch to be properly configured in advance. This early preparation of control signals reduces the setup time requirement while the modular logic gate structure manages the complexity through functional decomposition.
Data Source
AI summary
A low-power low-setup integrated clock gating (ICG) cell is disclosed. The disclosed ICG cell includes a NOR gate configured to receive an enable (E) signal and a test enable (SE) signal, and to output an EN signal. The ICG cell may include a complex gate configured to receive the EN signal and a clock (CK) signal, and to output a latched enable (ELAT) signal. The ICG cell may further include a NAND gate configured to receive the ELAT signal and the CK signal, and to output an inverted enabled clock (ECKN) signal. The ICG cell may further include an inverter configured to receive the ECKN signal from the NAND gate, and to output an enable clock (ECK) signal.