Clock Gating Circuit Topology for Lower Dynamic Clock Power
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Solution Overview
Problem
The semiconductor integrated circuit (IC) industry faces issues with clock signal synchronization and power consumption in clock trees, leading to performance errors and area inefficiencies as ICs become smaller and more complex.
Innovation Solution
A clock gating circuit is implemented, comprising a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor, which reduces the number of transistors toggled by the inverted clock signal, resulting in lower dynamic clock power consumption and reduced area occupancy compared to other clock gating cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a conventional clock gating circuit is used, then clock signal distribution and synchronization are achieved, but dynamic power consumption and area occupancy increase due to more transistors being toggled by the clock signal
Solution Approach 1:
The patent extracts and removes unnecessary transistors from the conventional clock gating circuit structure. By analyzing the clock gating functionality, the invention identifies and eliminates redundant transistor components that do not contribute to the essential clock gating operation, thereby reducing the total transistor count from 14 to 10 transistors while maintaining the required functionality.
Solution Approach 2:
The patent merges multiple transistor functions into fewer transistors. By combining the clock signal distribution, enable signal response, and output generation functions into a more integrated transistor arrangement, the circuit achieves the same clock gating effect with fewer discrete transistor components, reducing both area and dynamic power consumption.
2Area of stationary object
If a conventional clock gating circuit is used, then clock signal distribution and synchronization are achieved, but area occupancy increases due to more transistors
Solution Approach 1:
The patent extracts and removes unnecessary transistors from the conventional clock gating circuit structure. By analyzing the clock gating functionality, the invention identifies and eliminates redundant transistor components that do not contribute to the essential clock gating operation, thereby reducing the total transistor count from 14 to 10 transistors while maintaining the required functionality.
Solution Approach 2:
The patent merges multiple transistor functions into fewer transistors. By combining the clock signal distribution, enable signal response, and output generation functions into a more integrated transistor arrangement, the circuit achieves the same clock gating effect with fewer discrete transistor components, reducing both area and dynamic power consumption.
3Reliability
If more transistors are used in the clock gating circuit, then clock signal distribution coverage is improved, but dynamic power consumption increases due to more transistors being toggled
Solution Approach 1:
The patent extracts and removes unnecessary transistors from the conventional clock gating circuit structure. By analyzing the clock gating functionality, the invention identifies and eliminates redundant transistor components that do not contribute to the essential clock gating operation, thereby reducing the total transistor count from 14 to 10 transistors while maintaining the required functionality.
Solution Approach 2:
The patent implements a design where the clock gating circuit automatically responds to enable signals without requiring additional clock-toggled transistors. The enable signal directly controls the transmission gate, allowing the circuit to self-regulate clock signal passage based on operational needs, thereby reducing unnecessary dynamic power consumption from clock signal toggling.
Data Source
AI summary
A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.