Clock Gating Coupled Memory Retention Circuit for Leakage Reduction
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Solution Overview
Problem
High-performance integrated circuits face significant power consumption challenges due to high leakage current, particularly in SRAM, which is not effectively reduced by existing clock gating techniques, leading to increased total power consumption.
Innovation Solution
A memory retention circuit that detects when clock gating is enabled and automatically transitions memory modules to a retention power state, reducing both leakage and dynamic power consumption by power gating the periphery logic and optionally reducing the bit cell array voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock gating is enabled to reduce dynamic power consumption, then dynamic power is reduced, but leakage power remains high and is not effectively reduced
Solution Approach 1:
The memory module is segmented into two distinct parts: periphery logic and bit cell array. The patent applies different power management strategies to each segment - clock gating to the periphery logic and retention mode to the bit cell array. This segmentation allows independent control of power consumption in each component, enabling the periphery logic to enter low-power state while maintaining data in the bit cell array with minimal leakage power.
Solution Approach 2:
The patent applies local quality by implementing selective power gating - the periphery logic is placed in retention mode with reduced power supply while the bit cell array continues normal operation. This localized approach allows different regions of the memory module to operate in different power states simultaneously, optimizing overall power consumption while maintaining functionality.
2Productivity
If more SRAM is added to increase performance, then processing capability is improved, but total power consumption increases due to higher leakage current
Solution Approach 1:
The patent changes the power supply parameter for the periphery logic, reducing it from full operating voltage to a lower retention voltage when clock gating is active. This parameter change allows the periphery logic to maintain its state with minimal power consumption, enabling larger SRAM configurations without proportionally increasing total power consumption.
3Speed
If clock frequency is increased to improve performance, then switching rate is improved, but dynamic power consumption increases
Solution Approach 1:
The patent implements periodic action by enabling clock gating - the clock signal is periodically enabled and disabled based on whether the memory module is actively being accessed. When clock gating is enabled, the periodic clock transitions are suspended, reducing dynamic power consumption while maintaining the ability to resume normal operation when needed.
Data Source
AI summary
A hierarchy of interconnected memory retention (MR) circuits detect a clock gating mode being entered at any level of an integrated circuit. In response, the hierarchy automatically transitions memory at the clock gated level and all levels below the clock-gated level from a normal operating state to a memory retention state. When a memory transitions from a normal operating state to a memory retention state, the memory transitions from a higher power state (corresponding to the normal operating state) to a lower power state (corresponding to the memory retention state). Thus, in addition to the dynamic power savings caused by the clock gating mode, the hierarchy of MR circuits automatically transitions the memory modules at the clock gated level and all levels below the clock gated level to a lower power state. As a result, the leakage power consumption of the corresponding memory modules is reduced relative to prior approaches.