Clock Gating Control for Embedded Memory Sleep Power Saving
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Solution Overview
Problem
Existing embedded systems continue to consume power in power-saving modes due to operating clock circuits and internal memory, particularly in long signal paths.
Innovation Solution
Implement a clock controller circuit to manage clock and supply voltage gating, including a clock gating circuit to stop clock signals and a bus controller circuit to halt access requests, thereby reducing power consumption by transitioning components to sleep modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock circuits and internal memory continue operating in power-saving mode, then system reliability is maintained, but power consumption increases
Solution Approach 1:
The patent segments the system into multiple controllable blocks with independent clock gating. Different clock domains can be independently gated based on activity requirements, allowing partial power savings while maintaining functionality in active segments. The clock controller divides the system into gateable and non-gateable clock domains, enabling selective power management.
Solution Approach 2:
The patent implements dynamic clock gating control where the system can transition between different power-saving states based on actual activity. The clock controller dynamically adjusts which clock signals are gated, allowing the system to adapt its power consumption to actual operational needs while maintaining reliability when required.
2Use of energy by moving object
If clock signals are stopped to save power, then power consumption decreases, but system compatibility and reliability may be affected
Solution Approach 1:
The patent applies local quality by selectively gating clock signals only in specific domains where power saving is needed, while maintaining clock signals in domains requiring functionality. The clock gating circuit applies different control signals to different clock domains, allowing localized power management without affecting overall system compatibility.
Solution Approach 2:
The clock controller acts as an intermediary between the power management system and various clock domains. It receives power-saving requests and intelligently determines which clock signals to gate, translating high-level power management commands into specific clock gating actions that maintain system compatibility.
3Reliability
If long signal paths in clock circuits operate, then system functionality is maintained, but power consumption increases due to signal propagation
Solution Approach 1:
The patent extracts and gates clock signals in long signal paths when they are not needed for functionality. The clock gating circuit identifies and removes unnecessary clock signal propagation through long paths by applying gate control signals, eliminating the power consumption associated with these extended signal paths while maintaining essential functionality.
Data Source
AI summary
An embedded system includes a clock controller circuit, a clock gating circuit, and a bus controller circuit. The clock controller circuit is configured to set a memory control signal according to a sleep signal from a processor to control a first memory to enter a sleep mode and to set a clock control signal and a request signal according to the sleep signal. The clock gating circuit is configured to stop transmitting a plurality of clock signals to the processor and the first memory according to the clock control signal. The bus controller circuit is configured to stop sending an access request to the processor and the first memory according to the request signal.