Clock Gating Merging for Power-Efficient Microprocessor Design
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Solution Overview
Problem
In semiconductor design, implementing clock gating opportunities is complicated by routing constraints and power considerations, as not all identified clock gating opportunities are physically realizable or power efficient due to excessive power overhead and limited routing channels.
Innovation Solution
The method involves selecting initial clock gating functions, defining subsets, and creating super clock gating functions by existentially quantifying variables, sorting and selecting the most efficient ones to merge gated-clock domains, and modifying remaining functions to prevent overlap, resulting in a more power-efficient and physically realizable gate-level netlist.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple individual clock gating functions are implemented separately, then each gating function can be optimized independently, but the number of clock headers increases and routing complexity increases
Solution Approach 1:
The patent merges multiple individual clock gating functions into a single super clock gating function by combining the gating logic of multiple flip-flop groups. This reduces the number of clock headers from multiple individual headers to a single super clock header, thereby reducing routing complexity while maintaining the independence of each gating function's optimization through the systematic combination process
2Loss of energy
If more flip-flops are grouped into clock gating domains, then power consumption reduces, but routing constraints may prevent physical realization
Solution Approach 1:
The patent applies segmentation by dividing flip-flops into multiple groups based on their clock gating requirements, where each group can be independently analyzed and optimized. The systematic approach segments the overall gating function into manageable subsets that can be physically realized while still achieving significant power reduction through the merging of these segmented groups into super clock gating domains
3Measurement precision
If individual clock gating headers are used for each flip-flop group, then gating precision is maintained, but the number of clock headers and power overhead increases
Solution Approach 1:
The patent merges multiple individual clock gating headers into a single super clock header that serves multiple flip-flop groups. This consolidation reduces the total number of clock headers and associated power overhead while maintaining gating precision through the systematic combination of gating functions that preserves the essential timing control for each flip-flop group
Data Source
AI summary
A method and system of merging gated-clock domains in a semiconductor design includes producing, for each subset of clock gating functions in an initial set of clock gating functions, a set of quantified functions produced by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset. If the set of quantified functions are equal, selecting one as a super clock gating function and adding it to the set of super clock gating functions. The set of super clock gating functions are sorted according to a criterion and the best is selected and added to the set of final clock gating functions. The remaining super clock gating functions are modified to prevent flip-flops gated by the selected super clock gating function from being gated by remaining super clock gating functions.