Integrated Clock Gating Cell With Multi-Path Discharge
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Solution Overview
Problem
As semiconductor integrated circuits become more complex, the power consumption of flip-flops and clock gating cells remains high, affecting operating speed and efficiency, especially as operating frequency increases.
Innovation Solution
An integrated clock gating cell with multiple discharge paths, including a feedback inverter that performs both feedback and discharge functions, is designed to reduce power consumption and enhance operating speed by improving the time required for the output clock signal to activate after the input clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional clock gating cells are used, then the circuit can perform clock gating function, but the power consumption remains high
Solution Approach 1:
The clock gating cell is divided into multiple independent discharge paths (first discharge path through first NAND gate, second discharge path through second NAND gate, third discharge path through third NAND gate) that can operate independently. This segmentation allows the circuit to discharge the second node through multiple parallel channels, reducing the overall power consumption while maintaining reliable clock gating functionality.
Solution Approach 2:
The circuit dynamically selects which discharge path to use based on the states of enable signals and clock signals. The feedback inverter dynamically adjusts the discharge path selection by feeding back the state of the first node to control the third discharge path, allowing the circuit to adapt its power consumption characteristics to the current operating conditions while ensuring reliable operation.
2Productivity
If operating frequency increases, then the processing speed improves, but the power consumption and influence on chip operating speed increases
Solution Approach 1:
The clock gating cell uses periodic clock signals (CK and NCK) and enable signals (SE and E) to control the discharge paths in a periodic manner. This allows the circuit to efficiently manage power consumption at higher operating frequencies by enabling clock gating during inactive periods while maintaining high processing speed during active periods, thus improving productivity without proportionally increasing power consumption.
3Loss of time
If multiple discharge paths are added, then the activation time of output clock signal improves, but the device complexity increases
Solution Approach 1:
The feedback inverter serves multiple functions simultaneously: it provides feedback from the first node to control the third discharge path, it generates the control signal for the third NAND gate, and it helps coordinate the operation of multiple discharge paths. This multi-functionality reduces the need for additional dedicated control circuits, thereby limiting the increase in device complexity while still achieving reduced activation time through multiple discharge paths.
4Device complexity
If conventional single discharge path is used, then the device complexity is low, but the activation time of output clock signal is long
Solution Approach 1:
The single discharge path is segmented into three parallel discharge paths, each controlled by different enable signals and clock signals. This segmentation allows simultaneous discharge through multiple paths when conditions permit, significantly reducing the activation time of the output clock signal while maintaining manageable device complexity through systematic design of the control logic.
Data Source
AI summary
A clock gating cell includes an input logic/latch circuit, a keeper logic/signal generating circuit, and an output driver. The input logic/latch circuit generates an internal enable signal based on first and second input enable signals, and generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal. The keeper logic/signal generating circuit is connected between the first node and a second node, includes a feedback path feeding back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes first and second paths discharging the second node. The first and second paths are different. The second path is connected to the feedback path. The output driver generates an output clock signal based on the second internal signal.