Clock Gating Latch Using NAND Gates to Cut Dynamic Power
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Solution Overview
Problem
Conventional clock gating systems in portable devices consume significant power due to the power usage of clock gating cells, even when areas of the clock tree are not in use, leading to reduced battery life and increased power consumption.
Innovation Solution
A clock gating system utilizing a set-reset latch instead of a traditional pass-gate latch, incorporating a pair of cross-coupled NOT-AND (NAND) gates, which reduces the number of transistors and dynamic power consumption by minimizing the number of transistors that toggle with each clock signal transition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional pass-gate latch is used in clock gating circuit, then the clock gating function is achieved, but the number of transistors and power consumption increase
Solution Approach 1:
The patent merges the clock gating function with the latch circuit by integrating the clock signal directly into the set-reset latch structure. The clock signal controls the transparency of the latch through the gating element, combining what would traditionally be separate clock gating cell and latch components into a unified structure that reduces transistor count and power consumption.
Solution Approach 2:
The set-reset latch is designed to serve multiple functions: it holds the enable signal state (latch function), responds to clock transitions (clock gating function), and controls data transmission (multiplexer function). This multi-functionality eliminates the need for separate dedicated clock gating cells, reducing overall circuit complexity and power usage.
2Loss of energy
If clock gating is applied to turn off areas of clock tree, then power consumption in those areas is reduced, but clock gating cells still consume power
Solution Approach 1:
The patent extracts the clock gating function from separate dedicated clock gating cells and integrates it directly into the latch circuit structure. By embedding the gating functionality within the set-reset latch itself, the design eliminates the need for additional standalone clock gating cells that would consume power, while still achieving effective clock tree branch power reduction.
3Device complexity
If set-reset latch is used instead of pass-gate latch, then the number of transistors is reduced, but circuit design complexity changes
Solution Approach 1:
The patent segments the clock gating functionality into distinct operational phases: the set phase (when clock transitions from low to high), the reset phase (when clock transitions from high to low), and the hold phase (when clock remains stable). This segmentation allows the set-reset latch to be designed with clearly defined control signals and transition conditions, simplifying the overall design process despite the reduced transistor count.
Data Source
AI summary
A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.