Bimodal Disable Circuit for NBTI-Balanced Clock Gating
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Solution Overview
Problem
Integrated circuits, particularly clock distribution circuits, face uneven degradation of pFETs due to Negative Bias Temperature Instability (NBTI) and other degradation processes, leading to duty cycle distortions in clock signals.
Innovation Solution
A bimodal disable circuit that alternates the logic level of the output signal during disable cycles, ensuring that nFETs and pFETs of inverters alternate between conductive and non-conductive states, thereby distributing degradation evenly and preserving the duty cycle of propagated signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the input to the clock distribution circuit is selectively disabled to conserve power, then power consumption is reduced, but uneven degradation of pFETs occurs due to NBTI
Solution Approach 1:
The patent applies periodic action by inverting the disable signal at alternating intervals. When the clock distribution circuit is disabled, the disable signal is periodically inverted so that alternating inverters experience the disabled state at different times. This periodic inversion ensures that all pFETs undergo similar degradation over time, preventing uneven aging while still allowing power savings during disabled periods.
Solution Approach 2:
The patent implements dynamics by making the disable state dynamic rather than static. Instead of keeping the circuit continuously disabled or enabled, the system dynamically alternates the disable state between different inverters over time. This dynamic approach allows the circuit to adapt and distribute stress uniformly across all components, resolving the contradiction between power savings and uniform degradation.
2Manufacturing precision
If the clock transitioning is continuously enabled, then duty cycle accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent uses periodic action to alternate the disable state among different inverters. By periodically inverting the disable signal, the system ensures that each inverter experiences the disabled state for only a portion of the total time, maintaining overall duty cycle accuracy while enabling power savings during disabled intervals.
Solution Approach 2:
The patent applies parameter changes by modifying the temporal distribution of the disable state. Instead of maintaining a static enable/disable configuration, the system changes the timing parameters of when each inverter is disabled, ensuring that the average duty cycle remains accurate while allowing individual inverters to be powered down periodically.
3Loss of energy
If a single inverter is continuously disabled, then power is saved in that inverter, but duty cycle distortion occurs due to uneven pFET degradation
Solution Approach 1:
The patent resolves this contradiction by implementing periodic inversion of the disable signal. Instead of continuously disabling a single inverter, the system periodically switches which inverter is disabled, ensuring that each inverter gets disabled for only a fraction of the total time. This distributes the power savings and prevents any single inverter from suffering uneven degradation that would cause duty cycle distortion.
Solution Approach 2:
The patent applies segmentation by dividing the disable function across multiple inverters rather than concentrating it in one. By segmenting the disabling action across alternating inverters over time, the system distributes both the power savings and the degradation stress, preventing duty cycle distortion while still achieving overall power reduction.
Data Source
AI summary
Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.