Clock Gating Network Layout for Lower Latency Clock Distribution
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Solution Overview
Problem
Conventional clock circuits in digital integrated circuits suffer from excessive clock latency and high power consumption due to long clock signal propagation paths and uneven path lengths, which affect clock signal transmission and quality.
Innovation Solution
A clock circuit design featuring a buffer module and N clock gating cells with a tree-shaped H-shaped clock network structure, where the clock signal travels through only one level of clock gating cells, reducing latency and power consumption by ensuring equal path lengths and using integrated clock gating cells to enhance clock signal quality and duty ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional clock circuit structure is used, then the clock circuit can operate, but the propagation path of the clock signal becomes excessively long, resulting in relatively long clock latency and high power consumption
Solution Approach 1:
The clock circuit is divided into multiple independent clock domains, each with its own clock gating cell. The clock signal is segmented into different paths (first clock path and second clock path) that can be independently controlled, reducing the overall propagation latency in each segment while maintaining full coverage.
Solution Approach 2:
The patent introduces a new dimension of control by adding clock gating cells that can selectively enable or disable clock signals in different paths. This dimensional addition allows the circuit to optimize clock distribution by activating only necessary paths, thereby reducing effective propagation distance and power consumption without compromising functionality.
2Use of energy by stationary object
If a conventional clock circuit structure is used, then the clock circuit can operate, but the power consumption on each clock path becomes excessively high
Solution Approach 1:
The clock gating cells provide dynamic control over clock signal distribution. Based on operational requirements, the circuit can enable or disable specific clock paths, making the power consumption adaptive rather than static. This dynamic control allows the system to consume only the necessary power for active functional units.
Solution Approach 2:
Different clock paths are optimized independently with local clock gating control. Each clock domain can have its own gating strategy tailored to its specific requirements, allowing power-efficient operation in inactive regions while maintaining full performance in active regions.
3Measurement precision
If frequency division is performed by subtracting clock pulses, then the output clock frequency can be divided, but the clock path becomes longer and latency increases
Solution Approach 1:
The patent introduces clock gating cells as intermediary components between the clock source and functional units. These gating cells provide frequency division and selection functionality without requiring long subtraction-based pulse counting paths. The intermediary gating mechanism achieves frequency control with minimal propagation delay.
4Loss of time
If the clock signal propagation path is shortened, then clock latency is reduced, but the driving capability of the clock signal may be insufficient
Solution Approach 1:
The patent combines multiple functions into the clock gating cell: frequency division, path selection, and signal buffering. By merging these functions into a single integrated cell, the design achieves short propagation paths while maintaining sufficient driving capability through the combined effect of multiple functional elements within the gating cell.
Data Source
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AI summary
The present invention provides a clock circuit and a clock signal transmission method. The clock circuit includes a buffer module (110), N multiplexers (120), and N clock gating cells (130). The buffer module (110) includes an input end (111) and N output ends (112), and is configured to enhance a driving capability of a clock signal received by the input end, and output the clock signal whose driving capability is enhanced from the N output ends, and the N output ends are connected to data ends of the N clock gating cells one to one. Output ends of the N first multiplexers are connected to enabling ends (131) of the N clock gating cells one to one. Each clock gating cell (130) is configured to output a clock signal from an output end (133) according to a frequency division logic signal or a gating logic signal received by an enabling end from an output end of a corresponding multiplexer and the clock signal received by a data end from an output end of the buffer module. According to the technical solutions of the present invention, a clock path can be shortened, a transmission latency of a clock source signal can be reduced, and power consumption of a clock circuit can be reduced.